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Visitor
Posts: 5
Registered: ‎01-24-2013

Differential digital I/O with XADC header on MMP

Dear experts,

We are trying to develop a simple connection with AES3 signal to MMP with a baseboard.

The simplest solution seemed to connect the signal to the XADC header. The signal is expected to be differential.

However this UCF part (connections to P4.17 & P4.19):

NET "AUDIO_IN1" LOC = "D25" | IOSTANDARD = "LVDS_25";
NET "AUDIO_IN2" LOC = "G25" | IOSTANDARD = "LVDS_25";

or similar (connections to P4.17 & P4.18):

NET "AUDIO_IN1" LOC = "D25" | IOSTANDARD = "LVDS_25";
NET "AUDIO_IN2" LOC = "G25" | IOSTANDARD = "LVDS_25";

together with the differential buffer in the VHDL code:

  signalbuf_i : IBUFGDS
      port map (
    I => AUDIO_IN1,
    IB => AUDIO_IN2,
    O => din);

gives the error in XISE 14.3:

ERRORSmiley Tonguelace:1118 - The I/O components "AUDIO_IN1" and "AUDIO_IN2" are the P- and
   N-sides of a  differential I/O pair. The component "AUDIO_IN1" needs to be
   placed in a IOBM site and component "AUDIO_IN2" in the adjacent IOBS site
   within the same I/O tile. The following issue has been detected:
   All of the logic associated with this structure is locked and the relative
   placement of the logic violates the structure. The problem was found between
   the relative placement of IOB33V AUDIO_IN2 at site IOB_X0Y118 and IOB33V
   AUDIO_IN1 at site IOB_X0Y119. 
   It is possible   to allow location constraints to override this rule by
   setting the environment variable XIL_PAR_ALLOW_LVDS_LOC_OVERRIDE.

Phase 1.1  Initial Placement Analysis (Checksum:138e3) REAL time: 1 mins 26 secs

 

Is it possible to connect a differential digital signal to XADC header on MMP? What is the reccomended procedure?

Will it also work on the KC705 developement board (there is also one XADC header with similar configuration)?

 

PS The code seems to compile if the signals are set as a single-ended (LCMOS25).

 

Thank you a lot in advance for the help.

 

Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: Differential digital I/O with XADC header on MMP

The XADC header pins 17-20 are signle-ended GPIO pins and are NOT internally connected to the XADC block, so you cannot used them as differential analog inputs.

Visitor
Posts: 5
Registered: ‎01-24-2013

Re: Differential digital I/O with XADC header on MMP

Thank you for the prompt answer.

I don't need an analogic input. I need to connect a differential DIGITAL signal.

17-20 ports of XADC are seemed good to me exactly because they are not connected to XADC block.

However I didn't realize how to use them in the differential mode (please have a look at the first message).

Thank you in advance.

Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: Differential digital I/O with XADC header on MMP

You cannot use these pins as differetial pairs as ther are not copnnected to the differetial pairs of the FPGA on the Avnet MMP. You may want to take a look at the KC705 board schematics to see if these pins are connected to the FPGA differential pins.

Visitor
Posts: 5
Registered: ‎01-24-2013

Re: Differential digital I/O with XADC header on MMP

Thank you a lot for the answer. We'll try to use these pins as single-ended then.