02-04-2016 06:52 AM
I have a project based on 7A35T_Arty_Ethernetlite_LwIP which works correctly when loaded into the FPGA. It has additional fabric VHDL, and a highly-modified but simple and smaller version of the LwIP Microblaze application code. The BSP settings are the same as LwIP. I would like to know how I can load this project into flash so it runs on power-up. I have followed 7A35T_Arty_SREC_Bootloader, and that also works fine, but I can't seem to add qspi_srec_bootloader and qspi_srec_bootloader.bsp into my LwIP-based project following the steps in SREC_Bootloader: I get all sorts ofr build errors. Perhaps there is a way to generate an MCS file and program the flash from within Vivado?
Any help will be appreciated.
02-05-2016 12:11 PM
The following solved the problem:
1. The qspi_srec_bootloader application and BSP require an AXI Quad SPI, present in the Arty_SREC_Bootloader example, but not in Arty_Ethernetlite_LwIP. I added one to the block diagram, connected it to the AXI Interconnect, AXI Interrupt Controller, etc. The block diagram for the Arty_SREC_Bootloader is the example I followed.
2. Created external interface Qspi_flash and port qspi_flash_sck for the above.
3. Regenerated the block diagram (this project had it out-of-context)
4, Regenerated my HDL wrapper.
5. Synthesize, implement, and export hardware to the SDK.
In the SDK,
1. Add qspi_srec_bootloader and qspi_srec_bootloader_bsp as described in "SPI SREC Bootloader Example Design for the Arty Evaluation Board". It was necessary to reduce the qspi_srec_bootloader stack size in the linker to 0x220 following link errors indicating I had insufficient stack space. I wish I understood this better, and whether there's a better way to get rid of the linker errors without reducing stack size.
2. Followed the rest of the steps in the above document to generate the various .bit and .elf files.
3. Programmed the flash as described on pp. 49-54 of the above document.