03-03-2016 07:07 PM
I am going to build a simple serial transceiver working at around 500Mbps under the Xilinx Aurora 4 lane protocol, anyone can help to confirm the Arty hardware, software and IP support this idea, seems the Artix-7 35T GTP transceiver can do this.
03-04-2016 07:56 AM
03-05-2016 10:10 PM
Thanks for your reply and clarify.
As I mentioned, I want to evaluate a simplex aurora receiver at about 500Mbps, can you suggest some evaluation board on the shelf for me to start with? and after to select a cost effective FPGA model, maybe from artix-7 series to build my own board unit, since it is a personal trail at the movement, cost is the thing have to be considered...
Thanks & Best Regards!
09-04-2018 11:42 PM - edited 09-04-2018 11:44 PM
noticed that the FPGA used on the ARTY (CSG324) does not appear to have any of the GTP transceivers bonded.The FPGA used on the Basys3 (CPG236) looks to have (2) GTP transceivers bonded? This seems odd because Xilinx advertises them in quads, and doesn't mention anything about that specific package in the pinout documentation (see page 30 of Artix-7 pinout PDF, too large to upload). 1) Has anyone tried using these transceivers on the Basys3? Perhaps through a PMOD interface? 2) Is there a MRCC or SRCC pin available on one of the PMOD which is in the same clock region as one of the GTP transceivers? If It's true, I'll go ahead and order a Basys3.