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New Member
Posts: 2
Registered: ‎01-26-2014

DVIO CLK on KC705

Hi,

I just run into trouble by connecting the DVI out clk pin to the K7:

DVIO_CLK+ is C23 on FMC connector and pin E21 on K7 FPGA.

E21 is a N-side pin which is not intended to be a clock input for single ended clocks. The design will not route.

I can force it to accept this pin by setting CLOCK_DEDICATED_ROUTE to FALSE but this may cause some stability trouble.

Do you have experience on this topic and/or any recommendation?

 

Thanks.

New Member
Posts: 2
Registered: ‎01-26-2014

Re: DVIO CLK on KC705

Sorry, my fault. I mixed up video out modul and video in modul ... clk in on FPGA is on a P-side pin.

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: DVIO CLK on KC705

Scared me for a second there, glad to hear to sorted it out !

 

Regards,

 

Mario.