01-26-2014 09:15 AM
I just run into trouble by connecting the DVI out clk pin to the K7:
DVIO_CLK+ is C23 on FMC connector and pin E21 on K7 FPGA.
E21 is a N-side pin which is not intended to be a clock input for single ended clocks. The design will not route.
I can force it to accept this pin by setting CLOCK_DEDICATED_ROUTE to FALSE but this may cause some stability trouble.
Do you have experience on this topic and/or any recommendation?