Regular Visitor
Posts: 9
Registered: ‎05-01-2012

Communicate OV9715 with Xilinx ML605 FPGA board

[ Edited ]



I am now trying to communicate the OV9715 camera with my ML605 FPGA board via FMC module. And here are some questions.


1. Since the camera has no independent power supply, so the camera will be powered ON when the FPGA board is switch ON?

2. It can be seen from the datasheet of OV9715 that there are a system clock XCLK, which generate the PCLK for pixel synchronizaiton. However, I am wondering if I am required to provide the XCLK? I am puzzled because there is such pin on board (camera), but it can be seen from the datasheet that it seems the CAM{i}_XCLK is generated by a 27MHz clock. Do I need to provide the XCLK? What is the clock frequency of XCLK and PCLK?

3. There are many registers to be configured. However, I have no idea which ones must be configured for the camera to start giving pixels.

Can I just leave all the settings by default?
4. If the power is ON when the FPGA board is ON, and XCLK is generated automatically, what else are the necessary steps to make the camera starts working? Can I just turn ON the power can start receiving the pixels using self-created interface(HREF,DATA...)?

5. Is it possible for the camera to output 8-bit greyscale pixels instead of RGB?

Is it possible for someone to share a reference design (not the one using EDK with lots of functions included, only the interface to communicate with camera/related configurations would be really appreciated)?


Many thanks for any hint...


By the way, I am using ISE13.1.

Regular Visitor
Posts: 9
Registered: ‎05-01-2012

Re: Communicate OV9715 with Xilinx ML605 FPGA board


I have figured out some of the questions.

Since no Avnet emplyee is answering questions, here are some of the answers I regard as correct.


1. Yes

2. NO, The XCLK is automatically generated by the CDCE925 on Avnet FMC Module. The default XCLK is 27MHz.

3. Just use the default register settings.

4. Refer to datasheet for power up

5. Not sure yet, but may choose one of the the channels (Red for example) for testing.


I still have problem configuring the Registers of camera using VHDL based I2C interface.

If anyone has a VHDL based interface, can you please share it?


Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: Communicate OV9715 with Xilinx ML605 FPGA board



Sorry about the delay in my response.


Your answers to your questions are correct.


1. Based on a jumper setting on the FMC module, the camera will take its power from one of either:

    - 3.3V (from FMC connector)

    - 5V (regulated on FMC module from 12V from FMC connector)


2. CAM_XCLK is generated from the CDCE925 on the FMC module


3. The image sensor may generate pixels on power-up, but I would not rely on this to be a known state

    Since the image sensor's PLL has to be configured, the PCLK may not be stable or deterministic


4. The default power-on mode of the image sensor is not supported by our reference design,

    so I cannot guarantee this mode.


5. The image sensor has color filters (red, green, or blue) on top of each pixel.

    These filters, arranged in a bayer pattern, are permanent, and cannot be removed or de-activated.

    If interpreted as grayscale, the pixels will generate a grid which corresponds to the bayer pattern of the filters.

    You must perform Color Filter Array Interpolation to do anything useful with this raw image pixels.


I recommend that you start with the camera reference design from the Spartan 6 Industrial Video Kit

This design is not supported on the ML605, but some users on the forum have started an effort to port this to the ML605. 

See the following thread for more info: 


I do not have a VHDL based I2C interface available.  





Regular Visitor
Posts: 9
Registered: ‎05-01-2012

Re: Communicate OV9715 with Xilinx ML605 FPGA board

[ Edited ]

Hi Mario,


 I've been testing the camera based on :

Now I have encountered a few problems.


1. The returned RESOLUTION remains 0x0.

I checked the code using ChipScope and found that the PCLK(fmc_imageov_cam1_clk_pin) remains HIGH.

However, when checking using the osciloscope, the following ports are working properly and the PCLK is 47MHz and is stable:

 the PCLK pin on the camera, the H4 pin on FMC module and FPGA pin A10 on Xilinx Virtex-6 FPGA board. 


(I am using camera 1 instead of camera 2, and I've changed the UCF file accordingly:

Net fmc_imageov_cam1_clk_pin         LOC = A10; # FMC1 - H4  (CLK0_M2C_P)

Net fmc_imageov_cam1_pwdn_pin        LOC = L30; # FMC1 - C23 (LA18_N_CC)

Net fmc_imageov_cam1_rst_pin         LOC = F31; # FMC1 - D8  (LA01_P_CC)

Net fmc_imageov_cam1_frame_valid_pin LOC = K33; # FMC1 - C10 (LA06_P)

Net fmc_imageov_cam1_line_valid_pin  LOC = J34; # FMC1 - C11 (LA06_N)

Net fmc_imageov_cam1_data_pin[0]     LOC = L26; # FMC1 - D15 (LA09_N)

Net fmc_imageov_cam1_data_pin[1]     LOC = L25; # FMC1 - D14 (LA09_P)

Net fmc_imageov_cam1_data_pin[2]     LOC = G30; # FMC1 - C15 (LA10_N)

Net fmc_imageov_cam1_data_pin[3]     LOC = F30; # FMC1 - C14 (LA10_P)

Net fmc_imageov_cam1_data_pin[4]     LOC = H32; # FMC1 - H14 (LA07_N)

Net fmc_imageov_cam1_data_pin[5]     LOC = G32; # FMC1 - H13 (LA07_P)

Net fmc_imageov_cam1_data_pin[6]     LOC = K29; # FMC1 - G13 (LA08_N)

Net fmc_imageov_cam1_data_pin[7]     LOC = J30; # FMC1 - G12 (LA08_P)

Net fmc_imageov_cam1_data_pin[8]     LOC = H33; # FMC1 - D12 (LA05_N)

Net fmc_imageov_cam1_data_pin[9]     LOC = H34; # FMC1 - D11 (LA05_P)


By the way, the BIT file is generated using ISE instead of EDK, the EDK system is include in the ISE project as a component.

I am not sure if this may be the cause of the problem. But as my EDK always fail to generate BIT file when launched directly, I have to launch it from within ISE and generate the BIT file inside ISE. I think the only difference is that IO buffers are added to ports when generating the BIT file within ISE.


Besides, I also checked PG_C2M.

It says in Spartan®-6 Industrial Video Processing Kit EDK Reference Design Tutorial:

If the camera is detected, but a video resolution of 0 x 0 is detected, it may be possible that the voltage level translators are disabled. This can be caused by PG_C2M not being asserted high.

FMC – pin D1 : PG_C2M => expected to 2.5V

I probed pin D1 and the voltage is 3.3V. Would this cause any problem? Anyway, it is HIGH.



2. Since I don't need all the functions in the demo, I want to keep only three ip cores: the DDR MPMC for data storage, sg_i2c_controller_v6_plbw_0 for SCCB camera configuration, and ivk_video_det_0 for image resolution detection.

However, when I removed some of the ip cores, the I2C failed to program the camera.

Before removing the ip cores, when running the following sentence in SDK, the data on SDA port is : I2C address of I2C_MUX + Control signal (decides which I2C devices to be accessed).


mux_data = 0x0F;         // all I2C slaves are selected  

num_bytes =  pContext->pIIC->fpIicWrite( pContext->pIIC, FMC_IMAGEOV_I2C_MUX_ADDR, mux_data, &mux_data, 1);


After I removed some of the ip cores, the data on SDA is : I2C address of I2C_MUX (no control signal is sent out from FPGA)

So no I2C device can be accessed.

I thought that sg_i2c_controller_v6_plbw_0 is the only ip that is related to the configuration of camera. But it seems that there is another ip that works together with sg_i2c_controller_v6_plbw_0 so as to configure the I2C. 

I am wondering which IP it is...


3.The camera starts working when PWDN is set LOW.

After programming the board (but before running SDK), the PWDN is already set LOW and the camera starts working. I am wondering which ip(in EDK) is configuring the camera whenever the FPGA is programmed?


By the way, I am think of ordeing another camera with sensor 0V9215.

I am now using OV9715, however, the actually resolution is 640x400@30fps when displayed in RGB color mode (4pixels actually represent one pixel).

It says on the datasheet of OV9215 that the chroma is B/W but the output format is RAW RGB. I am wondering what is the actually resolution of OV9215.

Does the RAW RGB means that even the chroma is B/W for OV9215, it still requires 4 pixels to represent one pixel with interpolation used?

I am now in need of a camera that is able to work at 640x480@60fps B/W, and the camera should be compatible with the Dual Image Sensor FMC module (I need two cameras for the system), any recommendation?


Thanks for any hint.


Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: Communicate OV9715 with Xilinx ML605 FPGA board



Which sampling clock are you using for ChipScope ?

If you are using PCLK, then it is normal for PCLK to always appear 1 (you are sampling a clock with itself)


For PG_C2M, the ML605 schematic shows the DVI_GPIO1_FMC_C2M_PG being pulled up to VCC3V3,

so a 3.3V level is normal. 

As you mentionned, the important point is that this signal be HIGH, since it enables the voltage level translators.


There are two IIC controllers in the design:

1) FMC IPMI IIC chain

    - this IIC chain will detect the presence of the FMC module

    - the GPIO pins on this IIC chain are used for:

       - reset for DCM

       - FMC enable (this is used to enable the logic that drives outputs to the FMC connector)

    If you remove this IP core from your design, don't forget to connect the dcm_rst and fmc1_enable signals



    - this IIC chain is used to configure : I2C mux, DVI output device, OV9715 image sensors

    - the GPIO pins on this IIC chain are used for:

      - reset for DVI device

      - reset for I2C mux

      - reset for camera (CAM1_RST)

      - powerdown for camera (CAM1_PWDN)