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Avnet Employee (Star Contributor)
Posts: 469
Registered: ‎04-16-2009

FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

[ Edited ]

Hello,

I have posted a new Vivado 2014.4 design for the FMC-IMAGEON + VITA-2000 hardware.

This design supports the following FMC carriers:

- ZC702

- ZedBoard

- MicroZed 7020 SOM + MicroZed FMC Carrier Card

This design uses a new version of the VITA receiver, which has been split into two cores:

- onsemi_vita_spi (contains the SPI controller)

- onsemi_vita_cam (contains the LVDS de-serializer, etc...)

The reason for splitting the core into two components is to simplify things for a V4L2 Linux driver, which is currently being developed.

For this version of the design, the design files have been posted on the new Avnet github repository.

The attached document describes how to obtain the design files, and build the design with TCL scripts.

Regards,

Mario.

Regular Visitor
Posts: 2
Registered: ‎03-14-2015

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

[ Edited ]

Hi,

thanks for sharing this design! , I got the next error when I run the command : "source ./make_fmc_imageon_gs.tcl” in Vivado 2014.4 Tcl Shell

Requesting Tag

couldn't execute "git": no such file or directory

%Vivado

What is the correct way to setup the Tcl Shell before launch the build? .

greetings!

maurimum

 

Avnet Employee (Star Contributor)
Posts: 469
Registered: ‎04-16-2009

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

We (Avnet) have a tag option which can only be used internally, this is used to transfer the designs files to the public github repository.

Can you verify that the "tag=yes" option is NOT specifiied in the "set argv ..." command ?

Regards,

Mario.

 

Visitor
Posts: 2
Registered: ‎03-19-2015

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

Hello,

Thanks for sharing this reference design, I was able to test it with Vita Sensor and worked fine, but now I'd like to begin the deveploment for test my own design blocks, The first I did is modify this line command in the make.tcl file:

 

# if using for development, can set this to yes to just use the script
# to build your project in Vivado
if {[string match -nocase "yes" $close_project]} {
puts "Not Closing Project..."
} else {
set curr_proj [current_project -quiet]
if {[string match -nocase "" $curr_proj]} {
puts "Not Closing Project..."
} else {
puts "Closing Project..."
close_project
}
unset curr_proj
}

Is this step correct to build the vivado block design files, and begin my development? or which are the changes that I have to do in the script files?

greetins!!

milekro

Avnet Employee (Star Contributor)
Posts: 469
Registered: ‎04-16-2009

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

milekro,

You don't have to modify the make.tcl script.

If you want the project to remain open after being built by the scripts, you can add the "close_project=no" option in the make_fmc_imageon_gs.tcl script (or your custom build script).  To vew the project, type the "start_gui" in the TCL console to open the project.

Another option is to simply open the .xpr project with Vivado.

Regards,

Mario.

Visitor
Posts: 2
Registered: ‎05-28-2015

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

The build script ran smoothly and I was able to load both the program and the bistream onto my ZC702 Zynq.   It printed some output on the terminal indicating that it couldn't initialize the VITA sensor.

FMC-IMAGEON Initialization ...
Video Clock Synthesizer Configuration ...
HDMI Output Initialization ...
FMC-IMAGEON VITA Receiver Initialization ...
FMC-IMAGEON VITA SPI Config for 10MHz ...
FMC-IMAGEON VITA Initialization ...
VITA sensor failed to initialize ...

On my monitor I get a still frame of vertical bands of colored noise.  

When I open up the Vivado project, there is a critical warning that the design did not meet timing.   

Any ideas? 

 

 

 

 

 

 

 

 

Visitor
Posts: 2
Registered: ‎06-04-2015

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

Hello Mario,

First I would like to express my appreciation to this reference design you made. It is a great help to the project I am doing at the moment (I'm a student).

I was able to successfully rebuild the ref design, move the fmc imageon board to slot FMC1 and still get the satisfied video image. I am only interested in the camera input and don't really need the hdmi pass through input. 

Now for the need of my project, I would need to use at least 112 (or the best is 128) BRAMs. I saw that on this ref design 45 BRAMs are already in used.  There are only 140 BRAMs totally in z702 chip.

My question is whether I will be able to get the number of BRAM i want by removing the hdmi-input partition and still get the design to work ?

I know it involved the vcdma_0 block inside the block diagram which in turn lead to a on-screen display multiplexer. However this also involved many AXI interconnections that I am not very familiar with. Can you provide me a clean way to remove the partition cleanly so there are more BRAMs become available Smiley Happy

Looking forwards to hearing from you and thanks again for your work,

Joe.

 

Avnet Employee (Star Contributor)
Posts: 469
Registered: ‎04-16-2009

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

fabricGuy,

Can you confirm that you have the FMC module connected to the ZC702's FMC slot #2 ?

Can you confirm that you have the VITA camera connected to the FMC module ?

Regards,

Mario.

Visitor
Posts: 2
Registered: ‎05-28-2015

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

Hi Mario,

Yes, I can confirm that the FMC module is connected to the FMC slot #2 and the VITA camera is connected to the FMC module.

I discovered something bad on the sensor module.  VDD_18 is at 2.98V, not even close to 1.8V like it should be, which has probably damaged the sensor.     The other voltages are correct: VDD_pix and VDD_33 are at 3.3V, and the 5V test point is at 5.09V.

 

Thanks,

 

Ron

 

 

 

 

 

 

Regular Visitor
Posts: 3
Registered: ‎06-22-2015

Re: FMC-IMAGEON + VITA Getting Started design for Vivado 2014.4

I am trying the reference design with the ZC702 board. Following the instructions the project builds successfully, but I've seen severe timing violations in the implemented result. Most violations are from clk_fpga0 to vita_clk (the derived div 4 clock from video_clk). When I check the timing constraints in the XDC file, I see only the "video_clk" is mentioned as asynchronous to the clk_fpga0. So what about this vita_clk? Should it be set as asynchronous to the clk_fpga0 as well?

---

Below is the asynchronous timing constraints.

set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] \
                                                      -group [get_clocks clk_fpga_1] \
                                                      -group [get_clocks {n_3_serdesclockgen[0].ic}] \
                                                      -group [get_clocks video_clk] \
                                                      -group [get_clocks hdmii_clk]