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Regular Visitor
Posts: 2
Registered: ‎07-21-2014
Accepted Solution

Modifying ZVIK Reference Design for Two Cameras - IDELAYCTRL

[ Edited ]

Goal:

I have the Zynq-702 Video and Imaging Evaluation Kit (ZVIK) and was able to build the Targeted Reference Design without many issues under Vivado 2013.2.  My next step is to modify this design to accept an additional camera (from a second such kit).  I'm starting with the input side and have added an additional fmc_imageon_vita_receiver IP block as well as an additional v_vid_in_axi4s block for the second camera, and my goal at this stage is to multiplex the camera inputs into the rest of the video pipeline using a hardware switch to switch between cameras, which I believe I have accomplished in IP Integrator.

 

 

My Issue:

Synthesis of my design completes successfully.  However, in the implementation stage, I encounter an error in Vivado:

[Place 30-351] Design has more than one unlocked and ungrouped IDELAYCTRL instances. Please instantiate a delay controller (or use an existing one if delay values allow so) and apply appropriate IODELAY_GROUP or LOC constraints on the delay instances, or instantiate only one delay controller for the design without any IODELAY_GROUP or LOC constraints. The instances involved are: design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_iserdes_v5.vita_iserdes/generate_idelay.serdesidelayrefclk/IDELAYCTRL_INST[0].u_idelayctrl, and design_1_i/fmc_imageon_vita_receiver_2/U0/USER_LOGIC_I/VITA_CORE_I/vita_iserdes_v5.vita_iserdes/generate_idelay.serdesidelayrefclk/IDELAYCTRL_INST[0].u_idelayctrl

 

 

Attempted Resolutions:

After reading the error message and what few related resources I could find on the subject of IODELAY_GROUP (including Xilinx AR#39966 and friends, as well as this forum and the Xilinx forums),  I concluded that I need to group together the IDELAY instances within each of the two fmc_imageon_vita_receiver modules (to form two HIODELAY_GROUPs).  However, I've had a lot of difficulty doing so.

I tried adding constraints to the existing XDC file, like so:

set_property HIODELAY_GROUP iodgroup_1 [get_cells {design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_iserdes_v5.vita_iserdes/generate_datagen.datagen[0].db/iserdesgen[0].ic/IDELAY_K7_GEN.IDELAYE2_inst}]

(I had similar commands for each of the four datagen[] instances.)

 

However, each command yields the following error message in the place_design stage of implementation:

[Netlist 29-69] Cannot set property 'HIODELAY_GROUP', because the property does not exist for objects of type 'cell'. ["/opt/Xilinx/Vivado/2013.2/bin/ZVIK_TRD_X2/ZVIK_TRD_X2.srcs/constrs_1/new/design_1_impl.xdc":15]

 

The paths to the instance were found in the original constraints file and looking at the IP's VHDL source, they seem like they should be correct.  The examples I've found (including the Xilinx Vivado property reference) show commands of this format, using get_cells, so it doesn't seem like a type issue.

 

After reading this forum post:

http://forums.xilinx.com/t5/7-Series-FPGAs/The-constraint-about-IDELAYCTRL-and-IDELAYE2-in-source/td...

 

I decided that perhaps the IDELAYE2 instances didn't need to be in different groups, as long as there is only one instance of IDELAYCTRL in the entire design.  So, I've attempted to remove the instantiation of IDELAYCTRL from within the fmc_imageon_vita_receiver IP core, and push it out to the overall design file.  However, I need to connect the IDELAYCTRL reset signal to each fmc_imageon_vita_receiver core, which means adding an output to the receiver core.  I've had a lot of trouble trying to modify and repackage this core using the provided files, and I'm not sure that's the right way to proceed.

 

Any idea how to resolve this quickly? This seems like a fairly simple task, but I haven't found much information on the subject.  Thanks very much for any assistance you can offer!

 

Thanks,
Jack

Avnet Employee (Star Contributor)
Posts: 469
Registered: ‎04-16-2009

Re: Modifying ZVIK Reference Design for Two Cameras - IDELAYCTRL

[ Edited ]

Jack,

 

I was able to resolve this issue for a customer by assigning a location for each of the IDELAYCTRL primitives.

 

Here is how I did it for the ZC702 board:

- I built a design for FMC slot 1, and made note of the location for the IDELAYCTRL primitive

- I built a design for FMC slot 2, and made note of the location for the IDELAYCTRL primitive

 

Then I built the design with the two VITA receivers (one on each FMC slot), and assigned a fixed location for the two IDELAYCTRL primitives in the XDC constraint file:

 

set_property LOC IDELAYCTRL_X1Y1 [get_cells tutorial_i/fmc1_imageon_vita_color/fmc_imageon_vita_receiver_0/U0/vita_receiver_v2_0_S00_AXI_inst/VITA_CORE_I/vita_iserdes_v5.vita_iserdes/generate_idelay.serdesidelayrefclk/IDELAYCTRL_INST[0].u_idelayctrl]
set_property LOC IDELAYCTRL_X1Y0 [get_cells tutorial_i/fmc2_imageon_vita_color/fmc_imageon_vita_receiver_0/U0/vita_receiver_v2_0_S00_AXI_inst/VITA_CORE_I/vita_iserdes_v5.vita_iserdes/generate_idelay.serdesidelayrefclk/IDELAYCTRL_INST[0].u_idelayctrl]

 

This archive contains the three designs I mentionned in my response:

FMC_IMAGEON_2013_3_IP_Tutorials_20140307_zc702_solutions2.zip

 

Let me know if this helps !

 

Regards,

 

Mario.

Regular Visitor
Posts: 2
Registered: ‎07-21-2014

Re: Modifying ZVIK Reference Design for Two Cameras - IDELAYCTRL

[ Edited ]

Mario,

 

Thank you very much for your prompt assistance!  Your approach has worked nicely.  I can now get video from both FMCs. 

 

Regards,

Jack

Regular Visitor
Posts: 2
Registered: ‎11-02-2016

Re: Modifying ZVIK Reference Design for Two Cameras - IDELAYCTRL

Hi Mario,

 

I want to download you project, But the project can't do work.

I really need the project.

my hardward is zc702 and softward is vivado2015.4.

 

Regards,

 

Hank.