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Posts: 5
Registered: ‎05-29-2017

Modifying buses in FMC-IMAGEON design based on the tutorials for Vivado 2015.4

Hello,

 I've been able to get the basic passthru design working with a HDMI source and sink. I've broken out the AXI4S bus between the OSD block and the AXI4S to video converter. Should it be possible to remove the chroma data here with combinational logic? I've tried a slice/const/concat arrangement, this doesnt seem to work. Could this be causing timing problems?

 

Thanks,

 

Simon

Visitor
Posts: 5
Registered: ‎05-29-2017

Re: Modifying buses in FMC-IMAGEON design based on the tutorials for Vivado 2015.4

Solved this by removing the SDCARD from the Zedboard, having 2 sources of bit file  without fulling resetting was causing configuration problems with the FPGA. Removing and HDMI sinks and sources prior to running the application and reconnecting them also seemed to help.

 

Simon

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Posts: 5
Registered: ‎05-29-2017

Re: Modifying buses in FMC-IMAGEON design based on the tutorials for Vivado 2015.4

I've extended my design to include the XAPP890 sobel filter. In pass thru configuration it works fine. There is no output with this addtions.

I start by expanding the YUV4:2:2 signal to YUV4:4:4 -> then covert to RGB for the Sobel input. Its the reverse on the output of the Sobel filter which then feeds into the OSD block in the original design,

I did get these validation errors which I'm pretty sure I can ignore-

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /v_rgb2ycrcb_1/video_in(3) and /sobel_filter_0/OUTPUT_STREAM(4)
[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /sobel_filter_0/INPUT_STREAM(4) and /v_ycrcb2rgb_0/video_out(3)

 

ILA attached before the resample shows that the AXI4S bus has stopped streaming.

 

The software is a modified version of the 2015.4 software to configure the Sobel filter for restarting and the 1080p dimensions.

Any advice would be appreciated.

 

Simon

 

Visitor
Posts: 5
Registered: ‎05-29-2017

Re: Modifying buses in FMC-IMAGEON design based on the tutorials for Vivado 2015.4

Turns out the HLS core isn't emitting a SOF signal and the naming conventions are different between the HLS core and library cores so that not all bus signals are being matched up correctly. Bypassing the SOF and directly wiring the signal lines seems to be a work around until I check/modify the HLS core.

 

Thanks to Florent @ Xilinx for assitance with low level debug.

 

Simon

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