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Regular Visitor
Posts: 7
Registered: ‎12-28-2010

XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

[ Edited ]

Hi, I have problem making standard design for LX16 board with XPS_ETHERNETLITE core working with FMC-ISMNET card (DP83640 PHY). This problem can be characterized as "XPS_ETHERNETLITE core in PLB design and DP83640 PHY don't work together". XPS version is 13.1. ISMNET card has two DP83640 PHYs, LX16 board

has one DP83848 PHY. on-board DP83848 works fine with standard network designs for LX16 kit and also passes MII loopback test ("ls_emaclite_test_1" procedure, line 415 of \sys_test_0\src\ls_xemac_test.c file attached).

For ISMNET's DP83640 PHY fails MII loopback test with XPS_ETHERNETLITE core design. MDIO access to DP83640 works fine. All registers are readable and MII loopback mode sets fine. MII loopback test (in ls_emaclite_test_1) uses polling mode. it sends frame fine, but zero characters are received. In addition, I have a custom board with XC6SLX45 device and dual DP83640 PHYs, made with same schematic as ISMNET FMC card.

 XPS_ETHERNETLITE PLB design doesn't on that board either. Custom board has better access to pins, i probed it. Clocks and timing looks fine, except that for MII loopback PHY asserts RX_ER high for about 7 microseconds, so likely frame is discarded by MAC core. I haven't tried detailed Chipscope tests. It is not clear why DP83640 fails with XPS_ETHERNETLITE while DP83848 works fine.

 

Please see source code, UCF/MHS files and log files with PHYs register maps in attached ZIP file.  

C source code is derived from Avnet's and Xilinx examples and designs, there is nothing proprietary in it, please feel free to use it.

 

ISMNET FMC doesn't come with either XPS_ETHERNETLITE or XPS LL TEMAC designs, only with custom IP core industrial Ethernet designs for LX150T kit.

 

I think it would make sense to have XPS_ETHERNETLITE design running for ISMNET FMC either on LX16, SP605 or LX150T kit. I have SP605, ML605, LX16, ISMNET FMC kits in the lab (all except LX150T kit). i am almost sure that tracking this problem on either Spartan-6 kit and either PLB or AXI design will fix it.

 

Thank you.

 

 

Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

One potential problem that immediately comes to mind is that the DP83640 PHY on the ISMNET FMC module may be held in a power down state. 

 

Try adding this line to your MHS file:

PORT fpga_0_Ethernet_MAC_PHY_pwrdn_n_pin = net_vcc, DIR = O

 

And add this line to your UCF file:

Net fpga_0_Ethernet_MAC_PHY_pwrdn_n_pin LOC = A12 | TIG; //FMC1_LA17_N_CC

 

This solution assumes the ISMNET FMC module is plugged into the JX1 FMC connector on the Spartan-6 LX150T board and that you are attempting to use the J2 Ethernet connection on the module.  If you are using a different carrier board or the JX2 FMC connector on the LX150T you will need to edit the UCF LOC constraint accordingly.

 

--Tom

 

--
Tom Curran
Regular Visitor
Posts: 7
Registered: ‎12-28-2010

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

I checked whether PHY sits in reset or power down state from the start of debug.

In the log attached it shows DP83640 registers during tests ( C source and logs attached).

For DP83640 register 0x0 (BMCR) bit 11 shows whether device in power down state.

in this case bit 11 is clear during testing. Are you able to test FMC-ISMNET with LX150T

board? Thanks.

 

---------------------------------------------------------
LX16 board ISM FMC PHY DP83640
---------------------------------------------------------
  detected phy device at address 10;
  REG0x0 (BMCR): 3100;  REG0x1 (BMSR): 78C9;  REG0x10 (PHY_PHYSTS): 4000;

 

  REG0x16 (PHY_PCSR): 100;  REG0x19 (PHY_PHYCTRL): 8030;
  BMCR.LOOPBACK[ ];  BMCR.AUTO_NEG_ENABLE[x];  BMCR.ISOLATE[ ];
  BMSR.100X_FULL_DUP[x];  BMSR.100X_HALF_DUP[x];  BMSR.10T_FULL_DUP[x];  BMSR.10T_HALF_DUP[x];
  BMSR.UNIDIRECTIONAL[x];  BMSR.AUTO_NEG_COMPLETE[ ];  BMSR.LINK_STATUS[ ];
  PHYSTS.MDIX_MODE[x];  PHYSTS.RECV_ERR[ ];  PHYSTS.RMT_FAULT[ ];  PHYSTS.AUTO_NEG_COMPLETE[ ];
  PHYSTS.LOOPBACK_ENA[ ];  PHYSTS.DUPLEX_STATUS[ ];  PHYSTS.SPEED_STATUS[ ];
  PHYSTS.LINK_STATUS[ ];  PCSR.FIBER_MODE[ ];

 

  set phy loopback mode;

 

  REG0x0 (BMCR): 6100;  REG0x1 (BMSR): 78C9;  REG0x10 (PHY_PHYSTS): C;
  REG0x16 (PHY_PCSR): 100;  REG0x19 (PHY_PHYCTRL): 8030;
  BMCR.LOOPBACK[x];  BMCR.AUTO_NEG_ENABLE[ ];  BMCR.ISOLATE[ ];
  BMSR.100X_FULL_DUP[x];  BMSR.100X_HALF_DUP[x];  BMSR.10T_FULL_DUP[x];  BMSR.10T_HALF_DUP[x];
  BMSR.UNIDIRECTIONAL[x];  BMSR.AUTO_NEG_COMPLETE[ ];  BMSR.LINK_STATUS[ ];
  PHYSTS.MDIX_MODE[ ];  PHYSTS.RECV_ERR[ ];  PHYSTS.RMT_FAULT[ ];  PHYSTS.AUTO_NEG_COMPLETE[ ];
  PHYSTS.LOOPBACK_ENA[x];  PHYSTS.DUPLEX_STATUS[x];  PHYSTS.SPEED_STATUS[ ];
  PHYSTS.LINK_STATUS[ ];  PCSR.FIBER_MODE[ ];

 

  send test frame;

 

  REG0x0 (BMCR): 6100;  REG0x1 (BMSR): 78C9;  REG0x10 (PHY_PHYSTS): D;
  REG0x16 (PHY_PCSR): 100;  REG0x19 (PHY_PHYCTRL): 8030;
  BMCR.LOOPBACK[x];  BMCR.AUTO_NEG_ENABLE[ ];  BMCR.ISOLATE[ ];
  BMSR.100X_FULL_DUP[x];  BMSR.100X_HALF_DUP[x];  BMSR.10T_FULL_DUP[x];  BMSR.10T_HALF_DUP[x];
  BMSR.UNIDIRECTIONAL[x];  BMSR.AUTO_NEG_COMPLETE[ ];  BMSR.LINK_STATUS[ ];
  PHYSTS.MDIX_MODE[ ];  PHYSTS.RECV_ERR[ ];  PHYSTS.RMT_FAULT[ ];  PHYSTS.AUTO_NEG_COMPLETE[ ];
  PHYSTS.LOOPBACK_ENA[x];  PHYSTS.DUPLEX_STATUS[x];  PHYSTS.SPEED_STATUS[ ];
  PHYSTS.LINK_STATUS[x];  PCSR.FIBER_MODE[ ];

 

E0008 zero chars received;
E0040 phy loopback test failed;
---------------------------------------------------------

Regular Visitor
Posts: 7
Registered: ‎12-28-2010

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

I checked that device is powered up, also confirmed by LEDs and registers state.

Also device is not held in reset state and not in isolated state. They only difference

i saw between DP83640 and DP83848 PHYs is that DP83640 has Unidirectional

status bit on: BMSR.UNIDIRECTIONAL[x]; this bit can't be set or reset through MDIO

and it remains in '1' state. otherwise registers state between these two PHYs is

practically identical. my thought was that most likely both XPS_ETHERNETLITE and

DP83640 are IEEE802.3 compliant and tested. FMC-ISMNET cards work with

custom IP cores (Powerlink, EtherCAT) and also work fine on some MCU boards

from Freescale with standard MII interfaces. so my thought that may be after

reset some PTP functions turned on by default and these functions don't allow

regular Ethernet operation with XPS_ETHERNETLITE. and say when devices are

initialized through EPL software stack, these PTP registers are set correctly.

 

 

Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

Below is a known-good design built with the XPS and SDK 13.1 tools and targeting the S6LX150T + ISMNET FMC boards.  This design uses the PLB and xps_ethernetlite EMAC.  You can use this as a guide for targeting an Ethernetlite + ISMNET FMC design to your board of choice.  It is not documented and is not supported.

 

This link is only good for 5 days:

http://xfer.avnet.com/uploads/S6LX150T_FMC_JX1_ISMNET_J2_LwIP_Ethernetlite_edk13_1.zip

 

--Tom

 

--
Tom Curran
Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

Below is a known-good design built with the XPS and SDK 14.3 tools and targeting the S6LX16 + ISMNET FMC boards.  This design uses AXI and the axi_ethernetlite EMAC.  You can use this as a guide for targeting an Ethernetlite + ISMNET FMC design to your board of choice.  Assemble the LX16 + ISMNET boards and make the JTAG, UART, and Ethernet connections to the host PC.  Extract the zip file and open a command prompt in the <install>\demo folder and run the "run_demo.bat" batch file.  This will configure the FPGA with a "bootloop" bitstream and then download the lwIP software executable and webserver file system to the board and begin execution.  Follow the instructions in the UART terminal to operate the webserver and run the other lwIP applications.  This design is based on Xilinx XAPP1026.  It is not documented and is not supported. 

 

This link is only good for 5 days:

http://xfer.avnet.com/uploads/S6LX16_ISMNET_J2_LwIP_Ethernetlite_edk14_3.zip

 

--Tom

--
Tom Curran
Regular Visitor
Posts: 7
Registered: ‎12-28-2010

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

Thanks for quick response. you probably compiled design for S6LX16, but didn't test it.

I saw UFC constrains, these are generic XPS_ETHERNETLITE constrains that XPS

applies by default, except 10 ns OFFSET on TX_CLK, if i am correct. Otherwise it is

it is reference design for S6LX16 with PHY pinout changed from onboard to PHY#1

on FMC-ISMNET. I uploaded it to board using command line (SDK 14.3, run_demo.bat).

 

it doesn't work. symptoms are same as desribed previously: PC shows good 100 mbit link,

PHY#1 speed LED lighted up (power up state), but can't connect from PC using telnet.

activity LED on RJ-45 briefly blinks, shows that packets go in, but there is no connection.

 

I tested FMC-ISMNET with SP605 board. it went quite interesting, 1st that with SP605

FMC pinout basic it didn't met 6 ns MAXSKEW constraint for RX_CLK. so i changed it to

7.5 ns. so it didn't even met basic constraints for XPS_ETHERNETLITE core. but 

XPS_ETHERNETLITE design with FMC-ISMNET worked on SP605.

 

in addition to S6LX16 i have custom board designed with XC6SLX45 and dual DP83640

PHYs with schematics practically identical to FMC-ISMNET. I am able set RX_CLK, TX_CLK

MAXSKEW to 2.5 ns on that board and connection of FPGA to PHYs are straight 2" traces.

this design could work for GMII design. XPS_ETHERNETLITE doesn't work on that board

either. TX interface from FPGA to PHY works, i am able to send packets to PC and detect

them by Wireshark, but RX interface doesn't work.

 

so say if it works on LX150T and SP605 kits, but doesn't work with S6LX16 and custom

XC6SLX45 board, issue can be with RX interface timing that is affected by pin assignment

of different packages and design synthesis. Signal integrity or board routing issues and

FMC connector can't substantially affect 25 MHz MII interface timing. I think it is more of

FPGA synthesis and routing issue. it is usually encountered with RX interfaces timing

for GMII/RGMII designs. i haven't heard anybody having trouble with basic MII designs.

 

can you test it with S6LX16 board to confirm? Thanks.

 

 

 

 

Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

This design was indeed tested with a S6LX16 Rev A and ISMNET FMC Rev A board assembly.

 

Do you have the board assembly connected directly to your host PC, or through a router/switch?  Are you using a straight-thru or crossover Ethernet cable?  Please use a crossover cable and connect the board assembly directly to your host PC.  Also, configure the NIC on the host PC for 100Mbps, full duplex.  The axi_ethernetlite will not auto-negotiate correctly, especially if the host PC has a GbE NIC.  In this design that I supplied the lwIP software is configured to disable auto-negotiation and is hard set for 100Mbps, full duplex.  See XAPP1026 for more information about the lwIP software settings.

 

--Tom

 

--
Tom Curran
Regular Visitor
Posts: 7
Registered: ‎12-28-2010

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

I confirm it doesn't work on S6LX16 and ISMNET FMC Rev A. I am familiar with this test,

i run it many times on S6LX16. Direct connection to PC using crossover cable, PC NIC

speed set to 100 mpbs, full duplex. I uploaded BIT image without recompiling, it uploaded

successfully. Telnet and web page don't work - there is no link between FPGA and PHY,

MII loopback fails. i tested this FMC card with SP605, it works, it is new card. I believe

same problem was reported for Zynq 702 board. Thank you.

 

Regular Visitor
Posts: 7
Registered: ‎12-28-2010

Re: XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

[ Edited ]

this AXI_ETHERNETLITE design for S6LX16 and ISMNET FMC has error in UFC file:

-------------------------------------------

FMC PHY#1 (ETH1), UFC Errors:

-------------------------------------------

RXD[0] LOC = "N10" -> JX1.D26 -> ETH2_TX_D2;

TX_EN LOC = "V11" -> not mapped to JX1;

TXD[2] LOC = "P11" -> JX1.D27 -> ETH2_TX_D3;

-------------------------------------------

so ETH1.RXD[0] is mapped to EHT2_TX_D2 on FMC card;

 

i believe correct UFC constrains are:

-------------------------------------------

#--------------------------

# Ethernet FMC PHY#1

#--------------------------

Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC = R10 | IOSTANDARD = LVCMOS33; // JX1.G2

Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC = T9 | IOSTANDARD = LVCMOS33; // JX1.H4

Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC = F13 | IOSTANDARD = LVCMOS33 | IOBDELAY = NONE; // JX1.C18

Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC = A11 | IOSTANDARD = LVCMOS33 | IOBDELAY = NONE; // JX1.D18

Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC = F12 | IOSTANDARD = LVCMOS33 | PULLUP | IOBDELAY = NONE; // JX1.H28

Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC = M11 | IOSTANDARD = LVCMOS33 | IOBDELAY = NONE; // JX1.G27

Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC = U13 | IOSTANDARD = LVCMOS33 | IOBDELAY = NONE; // JX1.C26

Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC = C14 | IOSTANDARD = LVCMOS33 | IOBDELAY = NONE; // JX1.H26

Net fpga_0_Ethernet_MAC_PHY_col_pin LOC = F9 | IOSTANDARD = LVCMOS33 | PULLDOWN | IOBDELAY = NONE; // JX1.H20

Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC = E13 | IOSTANDARD = LVCMOS33 | IOBDELAY = NONE; // JX1.C19

Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC = G9 | IOSTANDARD = LVCMOS33 | TIG; // JX1.H19

Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC = V12 | IOSTANDARD = LVCMOS33; // JX1.H32

Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC = V16 | IOSTANDARD = LVCMOS33; // JX1.G31

Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC = U11 | IOSTANDARD = LVCMOS33; // JX1.H31

Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC = E12 | IOSTANDARD = LVCMOS33; // JX1.H29

Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC = N11 | IOSTANDARD = LVCMOS33; // JX1.G28

Net fpga_0_Ethernet_MAC_PHY_MDC_pin LOC = A7 | IOSTANDARD = LVCMOS33; // JX1.G19

Net fpga_0_Ethernet_MAC_PHY_MDIO_pin LOC = C7 | IOSTANDARD = LVCMOS33; // JX1.G18

Net fpga_0_Ethernet_MAC_PHY_pwrdn_n_pin LOC = A9 | IOSTANDARD = LVCMOS33 | TIG; // JX1.D21

 

#-- FMC PHY#1 rx clock

NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" PERIOD = 40ns HIGH 14ns;

OFFSET = IN 6 ns VALID 20 ns BEFORE "fpga_0_Ethernet_MAC_PHY_rx_clk_pin";

NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" MAXSKEW = 6 ns;

 

#-- FMC PHY#1 tx clock

NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" PERIOD = 40ns HIGH 14ns;

OFFSET = OUT 10 ns AFTER "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" ;

NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" MAXSKEW = 6 ns;

-------------------------------------------

 

but it is not only UFC, it is also likely same MII RX interface timing problem in synthesis.

  

ltest10