11-10-2009 09:27 AM
The target device will be the Spartan 6 but the evaluations board is not available at this time but is scheduled for delivery soon. However while working with the Virtex5 evaluation board to develop the system that will allow the MicroBlaze to directly read/write memory on the host PC. The following issues have been encountered:
None of the embedded examples found for the platform studio tool perform the direct access of host memory from the MicroBlaze processor, please let me know if there is one that may have been overlooked.
The embedded tool “Platform Studio” does not have an option for configuration of the Bar memory type, and size used to allow the host PCIe driver to configure the host address space.
Is there a method for performing this setup within the embedded tools that is not part of the "XPS core config" PCIe GUI?
Is there away to create the PCIe with core generator then import it into the embedded tool?
11-10-2009 09:45 AM
MicroBlaze can only access the host PC via the PCIe bridge IP in the EDK hardware library. If you look at the datasheet for this bridge, located in the <EDK>\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v4_02_a\doc folder, you will see that there are 2 parameters that you can use to set the number of BARs as well as the BAR size. You can simply set these parameters in your system.NHS file. These parameters consist of C_IPIFBAR_NUM and C_IPIFBAR_AS_0.
07-19-2013 12:38 AM
I want know if you resolved your problem. I am making project with sp605 my host linux is Linux 2.6.32-358.11.1.el6.x86_64 I tested the xapp1022 and xapp1052 but it'sn't work. I want make communication between a microblaze and host linux thaks the connector pcie.