Avnet Employee (Star Contributor)
Posts: 612
Registered: ‎04-20-2009

Sharing one PLL between two opposite-side MCBs

In the X-Fest memory presentation, it is explained that on the larger, 4-MCB chips, the PLL must be shared between MCBs on the same side of the device.  When you use MCBs on the opposite sides of the FPGA, you have the option of either sharing one PLL (and running at the same interface speeds) or use two PLLs for independent clock control.