12-04-2009 07:35 AM
As stated during X-Fest, Xilinx is working on an Application Note that will give designers a x32 memory interface using two MCBs and two x16 memory components. This logic is built from fabric and makes the interface appear internally at the User Logic to be a x32 interface. However, externally, the physical connections between memory chips and FPGA are completely independent. Each memory must independently be connected to the required I/O pins for each MCB. Address and control signals are NOT shared between the two chips.
I'll post again when this design is available.