03-01-2012 08:14 PM
I've got a file from 4room but I dont rememeber where it is.
Who can help me to get the paper for detail about this powerpoint?
I'm wonder about the stage of design DDR2 controller on FPGA spartan 3e. who can help me about that?
thanks a lot!
03-05-2012 08:04 AM
This document is a presentation delivered as part of Avnet's Speedway hands-on training program. It was based on Spartan-3A DSP, using the 1800A Starter Board. The techniques for Spartan-3E would be similar, but not identical.
There were several lab documents that were part of this training as well. You can get these through your local FAE, but be aware that these were based on ISE 9.2, and we are now on v13 software.
Have you considered looking at Spartan-6? It has a built-in memory controller and will be a much easier way to design a system with DDR2.