03-18-2010 06:54 PM
I have a development board with “Xilinx Virtex-5 XC5VLX110T-FF1136 FPGA”,and i need to use the SDRAM on it.
I got a problem about how to make the user constraints right.
Follows are part of .ucf.
NET "sys_clk_p" LOC = "E4" ; #Bank 4 AG22
NET "sys_clk_n" LOC = "D4" ; #Bank 4 AH22
NET "sys_clk_p" LOC = "AG22" ; #Bank 4 AG22
NET "sys_clk_n" LOC = "AH22" ; #Bank 4 AH22
why E4 is wrong,AG22 is right?
Thinks in Advence.
03-24-2010 03:26 PM
You can find an example user constraints file (UCF) file on the Avnet Design Resource Center.
Go to the product page for this board and click on "Support Files & Downloads". Then choose the V5LX110T Development Boot Loader Example Design.
Unzip the archive and find C:\lx110t_bootloader_edk11_2\Bootloader_Design\data\system.ucf