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Visitor
Posts: 1
Registered: ‎03-18-2010

Need Help on Virtex-5 LX110T SDRAM

I have a development board with “Xilinx Virtex-5 XC5VLX110T-FF1136 FPGA”,and i need to use the SDRAM on it.

I got a problem about how to make the user constraints right.

 

Follows are part of .ucf.

Error:

NET  "sys_clk_p"                                 LOC = "E4" ;       #Bank 4 AG22
NET  "sys_clk_n"                                 LOC = "D4" ;       #Bank 4 AH22

 

OK:

NET  "sys_clk_p"                                 LOC = "AG22" ;       #Bank 4 AG22
NET  "sys_clk_n"                                 LOC = "AH22" ;       #Bank 4 AH22

 

why E4 is wrong,AG22 is right?

Thinks in Advence.

Avnet Employee (Star Contributor)
Posts: 106
Registered: ‎07-07-2009

Re: Need Help on Virtex-5 LX110T SDRAM

You can find an example user constraints file (UCF) file on the Avnet Design Resource Center

 

Go to the product page for this board and click on "Support Files & Downloads".  Then choose the  V5LX110T Development Boot Loader Example Design.


 

Unzip the archive and find C:\lx110t_bootloader_edk11_2\Bootloader_Design\data\system.ucf