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spartan-3an interface with spansion s25fl204k flash for write/read the data bytes


Dear all.....
Here the verilog code and simulation model for write/read the single byte of data into the specific address byte of the flash s25fl204k memory using SPI Protocol which is 4-wire MOSI,MISO,CS,SCK are Configured for normal dual(I/O) pins of SPARTAN-3an FPGA.

HERE THE PROTOCOL BYTES I USED TO WRITE/READ THE DATA BYTES BASED ON DATASHEET OF THE ABOVE FLASH

BYTE READ

FOR MOSI( RISING EDGE OF SCK )

*Byte one - 03h(code for read)
*Byte 2,3,4 - address byte 24bit
*byte 5 -dont care

FOR MISO ( FALLING EDGE SCK )

*during byte 5 of MOSI

BYTE WRITE
*Byte one   - 06h(WRITE ENABLE)
*Byte 2 -02h (code for pag program)
*3,4,5 - address byte 24bit
*byte 6 -data = 8'h10101010

which simulation waveform is attached in the below jpeg picture

can any tell me this is the correct procedure for access the spansion flash with fpga .thak you

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 09:04:34 09/06/2014 // Design Name: // Module Name: xc3s50an_isf // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module S25FL204K_SPANSION_FLASH( input wire clock, input wire SO, input wire switch_write, input wire switch_read, output wire CS, output wire SCK, output wire SI, output reg MISO=1'bz ) ; wire SCK1; wire SCK2; reg MOSI_READ=0; reg MOSI_WRITE=0; reg CSB_R1=1'b1; reg CSB_R2=1'b1; reg CSB_START=0; reg [6:0] count_write=0; reg [6:0] count_read=0; reg [3:0] count_miso=0; reg [7:0] count_input=0; reg clk=0; reg out1=0; reg out2=0; reg flag=0; assign SI = ((CSB_R1==0)) ? MOSI_WRITE : MOSI_READ; assign CS = (CSB_R1==0 || CSB_R2==0) ? 1'b0 : 1'b1; assign SCK1 = ((count_write>1 && count_write<=9)||(count_write>=10&&count_write<51)) ? clk : 1'b0; assign SCK2 = ((CSB_R2==0)&&(count_read>1 && count_read<48)) ? clk : 1'b0; assign SCK = (CSB_START==1) ? SCK1 : SCK2; always @(negedge clock) begin count_input<=count_input+1; if(count_input<=49) clk<=1; if(count_input>49) clk<=0; if(count_input>=99) count_input<=0; end always @(posedge clk) begin if(switch_write==0) out1<=1; if(switch_write==1 && out1 ==1) begin CSB_R1 <=0; out1 <=0; end if(CSB_R1==0) CSB_START <=1'b1; if(CSB_START==1'b1) begin count_write<=count_write+1; case (count_write) //------------------------ 8'h06 + CSB_R1 HIGH LOW-------------- 1: MOSI_WRITE <= 1'b1; 2: MOSI_WRITE <= 1'b0; 3: MOSI_WRITE <= 1'b0; 4: MOSI_WRITE <= 1'b0; 5: MOSI_WRITE <= 1'b0; 6: MOSI_WRITE <= 1'b1; 7: MOSI_WRITE <= 1'b1; 8: MOSI_WRITE <= 1'b0; //--------------------------------------------------------------- 9: CSB_R1 <= 1'b1; 10: CSB_R1 <= 1'b0; //-------------------------02H (page program) 11: MOSI_WRITE <= 1'b1; 12: MOSI_WRITE <= 1'b0; 13: MOSI_WRITE <= 1'b0; 14: MOSI_WRITE <= 1'b0; 15: MOSI_WRITE <= 1'b0; 16: MOSI_WRITE <= 1'b0; 17: MOSI_WRITE <= 1'b1; 18: MOSI_WRITE <= 1'b0; //-------------------------ADDRESS 23-16 19: MOSI_WRITE <= 1'b0; 20: MOSI_WRITE <= 1'b0; 21: MOSI_WRITE <= 1'b0; 22: MOSI_WRITE <= 1'b0; 23: MOSI_WRITE <= 1'b0; 24: MOSI_WRITE <= 1'b0; 25: MOSI_WRITE <= 1'b0; 26: MOSI_WRITE <= 1'b0; //-----------------------------ADDRESS 15-8 -------- 27: MOSI_WRITE <= 1'b0; 28: MOSI_WRITE <= 1'b0; 29: MOSI_WRITE <= 1'b0; 30: MOSI_WRITE <= 1'b0; 31: MOSI_WRITE <= 1'b0; 32: MOSI_WRITE <= 1'b0; 33: MOSI_WRITE <= 1'b0; 34: MOSI_WRITE <= 1'b0; //-----------------------------ADDRESS 0-7 35: MOSI_WRITE <= 1'b0; 36: MOSI_WRITE <= 1'b0; 37: MOSI_WRITE <= 1'b0; 38: MOSI_WRITE <= 1'b0; 39: MOSI_WRITE <= 1'b0; 40: MOSI_WRITE <= 1'b0; 41: MOSI_WRITE <= 1'b0; 42: MOSI_WRITE <= 1'b0; //-----------------------------(data bits) 43: MOSI_WRITE <= 1'b1; 44: MOSI_WRITE <= 1'b0; 45: MOSI_WRITE <= 1'b1; 46: MOSI_WRITE <= 1'b0; 47: MOSI_WRITE <= 1'b1; 48: MOSI_WRITE <= 1'b0; 49: MOSI_WRITE <= 1'b1; 50: MOSI_WRITE <= 1'b0; endcase if(count_write >51) begin CSB_R1 <=1'b1; count_write <=0; CSB_START <=1'b0; end end end //////////////////////////////////////////////////////////////////////////////////////////////// always @(posedge clk) begin if(switch_read==0) out2<=1; if(switch_read==1 && out2 ==1) begin CSB_R2 <=0; out2 <=0; end if(CSB_R2==0) begin count_read<=count_read+1; case (count_read) //------------------------ 8'h06------------------------- 1: MOSI_READ <= 1'b0; 2: MOSI_READ <= 1'b0; 3: MOSI_READ <= 1'b0; 4: MOSI_READ <= 1'b0; 5: MOSI_READ <= 1'b0; 6: MOSI_READ <= 1'b0; 7: MOSI_READ <= 1'b1; 8: MOSI_READ <= 1'b1; //------------------------byte2 (page program) 9: MOSI_READ <= 1'b0; 10: MOSI_READ <= 1'b0; 11: MOSI_READ <= 1'b0; 12: MOSI_READ <= 1'b0; 13: MOSI_READ <= 1'b0; 14: MOSI_READ <= 1'b0; 15: MOSI_READ <= 1'b0; 16: MOSI_READ <= 1'b0; //----------------------- 17: MOSI_READ <= 1'b0; 18: MOSI_READ <= 1'b0; 19: MOSI_READ <= 1'b0; 20: MOSI_READ <= 1'b0; 21: MOSI_READ <= 1'b0; 22: MOSI_READ <= 1'b0; 23: MOSI_READ <= 1'b0; 24: MOSI_READ <= 1'b0; //-----------------------------(address)-------- 25: MOSI_READ <= 1'b0; 26: MOSI_READ <= 1'b0; 27: MOSI_READ <= 1'b0; 28: MOSI_READ <= 1'b0; 29: MOSI_READ <= 1'b0; 30: MOSI_READ <= 1'b0; 31: MOSI_READ <= 1'b0; 32: MOSI_READ <= 1'b0; //-----------------------------(data bits) 33: MOSI_READ <= 1'bx; 34: MOSI_READ <= 1'bx; 35: MOSI_READ <= 1'bx; 36: MOSI_READ <= 1'bx; 37: MOSI_READ <= 1'bx; 38: MOSI_READ <= 1'bx; 39: MOSI_READ <= 1'bx; 40: MOSI_READ <= 1'bx; endcase if(count_read >=41) begin CSB_R2 <=1'b1; count_read<=0; end end end //-----------------------------(data bits) always @(negedge clk) begin if (count_read >=33) begin count_miso<=count_miso+1; case(count_miso) 1:MISO <=SO; 2:MISO <=SO; 3:MISO <=SO; 4:MISO <=SO; 5:MISO <=SO; 6:MISO <=SO; 7:MISO <=SO; 8:MISO <=SO; 9:MISO <=SO; endcase if (count_miso >=9) begin count_miso<=0; end end end endmodule

 

s25fl204k_write_read.png