05-22-2017 07:09 PM
Hello,
We have a Kintex-7 MMP kit (AES-MMP-7K325T). We have finished a hardware design which includes a MicroBlaze and a software application for this design, now we want to program the bitstream and elf file to the MMP flash. The user guide of Kintex-7 MMP (5331-UG-AES-XK7MMP-G-V1_3) only provides how to do it by using ISE iMPACT, but we want to know how to do it by using VIVAD/SDK. We alos fond a document "5185-7A35T-Arty-SREC-Bootloader-VIV2015-2-V1" which described how to create a bootloader for Arty board, but it is for a QSPI flash.
Is there any tutorial for programming flash on Kintex-7 MMP by using VIVADO/SDK? or any document like "5185-7A35T-Arty-SREC-Bootloader-VIV2015-2-V1" but for programming on a BPI flash?
Best,
bj
Solved! Go to Solution.
05-22-2017 07:42 PM
05-28-2017 04:26 AM
Thank npoureh for the information. I've done the bootloader example. But in that example, it only shows how to generate a bootloader application and run it as launched on hardware. It lacks futher instructions about how to integrate the bootloader elf with FPGA bitstream and to download the integrated bitstream to the board. Alos it lacks how to setup constraints properly for BPI configuration to generate the bitstream for the Kintex-7 MMP. So this example design does not solve our problem.
I consulted the following reference:
and made some progress. At Vivado side, I used following constraints for BPI configuration to create the bitstream for Kintex-7 MMP:
set_property CONFIG_VOLTAGE 2.5 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE TYPE2 [current_design]
set_property CONFIG_MODE BPI16 [current_design]
At SDK side, I did following steps:
So far, the MMP worked fine. I saw the bootloader was working after FPGA being programmed, and my application being loaded successfully by bootloader. Following message showed at terminal.
SREC Bootloader
Loading SREC image from flash @ address: 60600000
...
Executing program starting at address: 00000000
Next, I run "Program Flash" again to write the download.bit into flash (the offset was set as 0x00000000), then turned off and turned on the MMP power. The bootloader looked work after MMP power on, but I got an error message:
SREC Bootloader
Loading SREC image from flash @ address: 60600000
ERROR: Error while reading an SREC line from flash
If I re-run "Program FPGA" to write FPGA bitstream with bootloader elf as the step 3 shown above, the design was work fine again.
Can anyone helps on this "Error while reading an SREC line from flash" problem?
best,
bj
05-29-2017 06:23 AM
Hi,
I find a solution to solve "Error while reading an SREC line from flash" problem. It is due to the failure of bitstream booting in synchronous mode. The details can be found in the "VC709 BPI unreadable after boot" topic in Xilinx community forms (https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/VC709-BPI-unreadable-after-boot/td-p/566033).
In my case, I modifed the BPI configuration constraints as follows
set_property CONFIG_VOLTAGE 2.5 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE DISABLE [current_design]
set_property CONFIG_MODE BPI16 [current_design]
The modifications are labeled by bold font. Then we re-generate the bitstream file by using these constriants on Vivado. The download.bit file integrated by this new bitstream and bootloader elf is work fine after it being programmed into the MMP flash.
best,
bj