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Avnet Employee
Posts: 1
Registered: ‎04-19-2009

Avnet S6LX150T Development Board AXI PCIe Endpoint Design

I have been working with the development kit and I have made some headway.

 

I am currently trying to get our development board to connect to a PC using the PCIe slot.

I am following a guide called "Avnet S6LX150T Development Board AXI PCIe Endpoint Design" which I found here :

https://www.em.avnet.com/Support%20And%20Downloads/s6lx150t_pcie_design_ise_14_2.zip

 

I have followed the guide and am able to compile the code and load the resulting .bit file into the FPGA.

 

However I am not able to see the card in the PCI space.

I am checking this by using the "lspci" command in linux.

 

I have found one mistake in the guide on page 17.

It says "Modify the

\PCIe_Reference_Design\s6_pcie_v2_4\example_design\xilinx_pcie_1_lane_ep_xc6slx150t-fgg676-3.ucf

file and assign pin H25 to the sys_reset_n signal. Save and close the UCF.

I have found according to the schematic of the development board that the pin should actually be V20.

 I can also confirm that the FPGA is getting the 125 MHz clock.

Despite this I am still not able to see any results.

Is it possible for you to help me, or put me in touch with someone familiar with the development board?