06-01-2010 11:14 AM
Although Xilinx doesn't offer an IP core generically for convolution, an FIR filter essentially performs convolution of an input series of samples with a set of coefficients. Customers who ask for convolution, auto-correlation and cross-correlation can sometimes use the Xilinx FIR Compiler. Auto-correlation (correlation of an input sequence with itself) requires you to dynamically reload coefficients of the FIR. If you are convolving an input sequence with a static vector, then using FIR Compiler is straightforward. If you are convolving to moving sequences, then you will have to take into account the filter reload time. The Xilinx FIR Compiler v5.0 core takes N+1 clock cycles to reload, where N is the number of coefficients (taps).
More information on the Xilinx FIR Compiler can be found here.
Avnet has several development kits available to prototype these and many more DSP algorithms.
For cost-sensitive applications, look at the Avnet Spartan-6 FPGA DSP Kit
For DSP applications requiring the highest performance available, look at the Avnet Virtex-6 FPGA DSP Kit
01-19-2011 01:34 AM
01-27-2011 10:21 AM
There could be a number of issues here. The best and quickest test is sending a unit impulse into the filter. This should produce the filter coefficients at the output - the so-called "impulse response" of the filter.
Have you verified that the enable pin on the filter core is active? Have you run the simulation long enough to account for filter latency? If you filter coefficients are extremely small fractional values, then sometimes you need to send a large-valued impulse into the filter in order for samples to survive the multiply with tiny fractional numbers.