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Visitor
Posts: 1
Registered: ‎05-25-2011

Reloading filters

Hi,

 

I'm new to VHDL and I'm having trouble getting the reloadable coefficients working for the FIR Compiler 5.0. I have a number of identically structured bandpass filters that I want to change between based on what a user register changes to.

 

I've included my logic/code below. I am using a Pentek card with a Virtex 6 FPGA. I am having trouble with having the card acquire as usual. I'm wondering if it might be due to my misunderstanding of how the FIR compiler works or if it is a timing issue. I've basically included in my .coe file, two sets of filter coefficients, and selected the reloadable coefficient option.

 

Thanks in advance for the help; it's greatly appreciated. If there is anything I can clarify, I would be glad to do so.

 

Regards,

 

dlui

 

=================================================================================


begin

    band_pass: bandpass
        port map (
            clk => ADC_CLK,
            nd => nd_signal,
            filter_sel => filt_sel,
            coef_ld => coef_load,
            coef_we => coef_write,
            coef_din => coeff,
            coef_filter_sel => coef_filt_sel,
            rfd => rfd_signal,
            rdy => rdy_signal,
            din => ADC_DATA,
            dout => bandpass_out);
            
-- Envelope Detection with Bandpass filtered data --

    max <= x"7FFF";
    min <= x"8000";
    
    -- Generate Write Ready signal from the write enable.
    process(PCIE_CLK, LRST_N)
        begin
        if (LRST_N = '0') then
            reg_wr_en       <= '0';  
            reg_wr_addr     <= (others => '0');  
            reg_wr_be       <= (others => '0');  
            reg_wr_data     <= (others => '0');  
            reg_wr_rdy         <= '0';
        elsif rising_edge(PCIE_CLK) then
                reg_wr_addr     <= WR_ADDR;
                reg_wr_en       <= WR_EN;
                reg_wr_be       <= WR_BE;
                reg_wr_data       <= WR_DATA;
                WR_RDY        <= WR_EN;
          end if;
    end process;

    -- Generate Read Ready signal from the read enable.
    process(PCIE_CLK, LRST_N)
    begin
        if (LRST_N = '0') then
            reg_rd_en      <= '0';
            reg_rd_addr    <= (others => '0');
            RD_RDY            <= '0';
            elsif rising_edge(PCIE_CLK) then
                reg_rd_en           <= RD_EN;
                reg_rd_be           <= RD_BE;
                reg_rd_addr            <= RD_ADDR;
                RD_RDY               <= reg_rd_en;
            end if;
    end process;
    
    process(PCIE_CLK)
      begin
          if rising_edge (PCIE_CLK) then
                if (conv_integer(reg_wr_addr) = 0) then
                    if (reg_wr_en = '1') then
                        reg   <= reg_wr_data;
                    end if;
             end if;
            end if;

        end process;      
    
    coeff_load: process(ADC_CLK)
    variable prev_data : std_logic_vector (15 downto 0):= (others => '0');
    begin
        if (rising_edge(ADC_CLK)) then
            if (prev_data /= ADC_DATA) then
                nd_signal <= '1';
                prev_data := ADC_DATA;
            else
                nd_signal <= '0';
            end if;
            
            if (coef_load = '1')then
                coef_load             <= '0';
            elsif(reg(0) = '0') then    
                coef_load             <= '1';
                coef_filt_sel         <= "0";
            elsif (reg(0) = '1') then
                coef_load             <= '1';
                coef_filt_sel         <= "1";
            end if;
            
    
        end if;
        
    end process coeff_load;
    
    
    -- Restrict the output of the bandpass filter
    compare_band: process (bandpass_out, max, min)
    begin        
        if (bandpass_out >= "0"& max) then
            bandpass_mod     <= max;
        elsif bandpass_out <= "1" & min then
            bandpass_mod      <= min;
        else
            bandpass_mod      <= bandpass_out(15 downto 0);
        end if;
    end process compare_band;
    
    USER_I_DATA <= bandpass_mod(15 downto 0) & x"0000";

    USER_DVAL   <= INPUT_DVAL;

    USER_INTERRUPT_OUT <= '0';

-------------------------------------------------------------------------------

end Behavioral;

Regular Contributor
Posts: 46
Registered: ‎07-09-2009

Re: Reloading filters

A couple of good coding documents that can be found on the Xilinx website are the XST User Guide and the "Synthesis and Simulation Design Guide".  The links below should take you to these documents.

 

XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices

Describes the XST synthesis tool, including instructions for running and controlling XST, discusses coding techniques for designing circuits using HDL, and gives guidelines to leverage built-in FPGA optimization techniques for Virtex®-6, Spartan®-6, and 7 series devices.

Synthesis and Simulation Design Guide

Designing Field Programmable Gate Arrays (FPGA devices) with Hardware Description Languages (HDLs).