Regular Contributor
Posts: 23
Registered: ‎05-30-2009

Flash at DSP configuration

Regular Contributor
Posts: 23
Registered: ‎05-30-2009

Re: Flash at DSP configuration


I do not understand something:

How does the EMIF know the flash parameters uppon CONFIGURATION?

There is a need to write to special registers of the EMIF controller in order to communicate with flash, how uppon reset does the EMIF knows the parameters?

If i change the boot flash to another parrallel flash, which steps should i do in order to make the configuration steps successful?


Thank you

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: Flash at DSP configuration



On the DaVinci board, the SW9[5:1] and SW10[4:1] set the DM6437's boot mode.

For more information on the DM6437's boot modes, refer to "Using the TMS320DM643x Bootloader"


For the parallel flash device, the Asynchronous 8 bit mode is used.

The default settings and the timing diagrams for the EMIFA interface is documented in the DM6437 data sheet.


When using a AIS (Application Image Script) bootmode such as EMIFA ROM Fast Boot With AIS (BOOTMODE[3:0] = 0100b, FASTBOOT = 1),

then the PLL, EMIFA, and DDR configuration registers are configured via the binary image.

This mechanism is called the "Function Execute Command", and consists of the "PLL Config", "EMIF Config", and "DDR Config" functions.

For more information on this mechanism, refer once again to "Using the TMS320DM643x Bootloader"