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Regular Contributor
Posts: 23
Registered: ‎05-30-2009

SCHEMATIC QUESTION

Hi

in page 20 of the schematic it says DNP  near FPGA DDR ADRESSA and near CS, WE

does it mean to not put those resistros?

 

 

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: SCHEMATIC QUESTION

These resistor terminations were added to the schematic assuming a worst case situation.

An IBIS simulation was performed showing that they weren't necessary.

They are still on the design, but are not populated.

 

For more information on this part of the design, refer to UG454 (Spartan-3A DSP Starter Platform User Guide).

The memory design for the DaVinci board is based on the Spartan-3ADSP 1800A Starter Kit.

 

Regards,

 

Mario.

Regular Contributor
Posts: 23
Registered: ‎05-30-2009

Re: SCHEMATIC QUESTION

Hi

 

in AN086 "http://www.nuhorizons.com/application_notes/application.asp?id=17"  Interfacing Micron DDR2 Memories to Xilinx Spartan-3A/AN FPGA it is suggested to use a loop_back signal (the bottum of the attached image),  but i do not see it on the davinchi schematic?

 

regards,

Assaf

untitled3.JPG
Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: SCHEMATIC QUESTION

Assaf,
  
Look at page 17 of the schematics.  The nets CLK_FB_MB and MB_FB_CLK are implementing the MB loop you are looking for.
The MB loop was implemented on the 1800A board to support the OPB_DDR2 controller, which was last used with EDK 9.1.

I would also draw your attention to the RST_DQS_DIV loop, which is also on page 17 of the schematics.

The RST_DQS_DIV loop is used for MIG-based controllers and for MPMC in EDK 9.2 and later.

 

The criteria for how the loops are implemented are different for the old OPB controller compared to MIG,

which is why we implemented two different loops.

  
Regards,
  
Mario
Regular Contributor
Posts: 23
Registered: ‎05-30-2009

Re: SCHEMATIC QUESTION

Hi Mario,

 

I'm  a little bit confused. what should i implement now? (with edk 11.3)

 

Regards,

Assaf

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: SCHEMATIC QUESTION

Assaf,

 

If you want to be able to support all IP cores (even older one), implement both.

 

However, with the 11.3 tools, you only need to implement the RST_DQS_DIV loop.

 

Regards,

 

Mario.

Regular Contributor
Posts: 23
Registered: ‎05-30-2009

Re: SCHEMATIC QUESTION

Thank you

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: SCHEMATIC QUESTION

My pleasure !

Regular Contributor
Posts: 23
Registered: ‎05-30-2009

Re: SCHEMATIC QUESTION

Hi Mario,

More questions:

on page 10 of the user guide,"

 

60-ohm* pull-up resistor to the termination supply at the split-point of shared signals (control, address)" 

 

1. sstl 18 determines that we do need to put pullup resistors there to vtt. how come you didn't populate it?

2. In which case should i populate it and when not? 

3. how does the 60 ohm value was calcualted?

4. if i were to use only ONE sdram component instead of 2, shouldn'y i needed to populate the pull up resistors?

 

Regards,

Assaf

 

 

 

 

 

Highlighted
Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: SCHEMATIC QUESTION

Assaf,

 

This level of detail was coverred in our X-fest memory course, as well as out DDR2 speedway.

I recommend that you contact the local Avnet FAE to get access to this course material.

 

Regards,

 

Mario.