12-01-2009 02:42 PM
These resistor terminations were added to the schematic assuming a worst case situation.
An IBIS simulation was performed showing that they weren't necessary.
They are still on the design, but are not populated.
For more information on this part of the design, refer to UG454 (Spartan-3A DSP Starter Platform User Guide).
The memory design for the DaVinci board is based on the Spartan-3ADSP 1800A Starter Kit.
12-02-2009 05:11 PM
in AN086 "http://www.nuhorizons.com/application_notes/application.asp?id=17" Interfacing Micron DDR2 Memories to Xilinx Spartan-3A/AN FPGA it is suggested to use a loop_back signal (the bottum of the attached image), but i do not see it on the davinchi schematic?
12-03-2009 08:20 AM
The RST_DQS_DIV loop is used for MIG-based controllers and for MPMC in EDK 9.2 and later.
The criteria for how the loops are implemented are different for the old OPB controller compared to MIG,
which is why we implemented two different loops.
12-03-2009 10:17 AM
If you want to be able to support all IP cores (even older one), implement both.
However, with the 11.3 tools, you only need to implement the RST_DQS_DIV loop.
12-05-2009 12:46 PM
on page 10 of the user guide,"
60-ohm* pull-up resistor to the termination supply at the split-point of shared signals (control, address)"
1. sstl 18 determines that we do need to put pullup resistors there to vtt. how come you didn't populate it?
2. In which case should i populate it and when not?
3. how does the 60 ohm value was calcualted?
4. if i were to use only ONE sdram component instead of 2, shouldn'y i needed to populate the pull up resistors?
12-09-2009 08:51 AM
This level of detail was coverred in our X-fest memory course, as well as out DDR2 speedway.
I recommend that you contact the local Avnet FAE to get access to this course material.