in dm6437 datasheet (SPRS345D) section 6.7.1 it is written that external EMI filter must be added to pllpwr18, but i do not see it on schematic? could you tell where it is, and if it is not there could you explain why not? attached picture 1
in dm6437 datasheet (SPRS345D) section 6.6.2 and 6.7.4 it is written that the clock source must meet the timing requirments in table 6-19. the duty cycle aloud in that table is 45%-55% but your clock source U32-Fox F510L-27.000MHz is 45%-60%, could you pleas verify that it is ok? see picture 2
Is the dsp configuration using parallel flash for the DSP supports 8MB or 16 MB? According to jumper settings on the board, AEAW[2:0] is 100b,so the maximum address is EM_A, acording to datasheet (see picture 3 of table 3)
Next, acording to schematice - see picture 4 there are 23 adress bits, incliding EM_A so i do not understand if EM_A is part of the configuration or not?
In the user guide it is written in p29 "EMIFA ROM Direct Boot1 supported by an Intel 28F128J3 16MB NOR Flash (BOOTMODE[3:0] = b0100)" but if we use AIS then it is not direct boot, but "EMIFA ROM Fast Boot With AIS (BOOTMODE[3:0] = 0100b, FASTBOOT = 1)", so i don't understand, is that a mistake in the user guide? do we use direct boot or fast boot with AIS?