02-03-2012 03:26 AM
I'm still getting errors during build in SDK 13.1. It seems something is wrong with the includes. I think I've done everything correct so far according to the instructions above. I don't want to start digging into the code and make changes before I have a working code. Please help. I attach all the project files.
02-03-2012 07:43 AM
I believe that your issues are related to using a C++ project (ie. g++ compiler).
This source code was validated within a C project.
Please create a new "Xilinx C project", copy your source files over, and re-build.
02-07-2012 12:50 PM
I am also having trouble getting the video demonstration compiled and running. The project tree I started with is from the S6 OMAP dev kit, but it looks like much of the source is common. I have it mostly compiled as a new C project with the appropriate libraries included (I believe), but still get the error:
If I add
to the main routine (and make a local copy of fmc_iic_sg.c - for some reason it isn't finding it), I can at least get it to compile and run. It gets to the line:
and then restarts. Probably not coincidentally, this is the line where the undefined reference/added variable is used.
I've made a few other changes, because I trimmed the XPS core down to what I will actually need for my project, but hopefully those changes are not related.
I am using version 12.3 of the tool set because that was what the reference design I was given was based on. If there is a newer reference design for the OMAP dev kit, I am not opposed to switching tool versions.
Any pointers on what I could be doing wrong or what to look at would be appreciated. I can provide my project, but would request guidance as to what files to include.
02-07-2012 02:19 PM
Unless you have two instances of the SG_I2C_CONTROLLER_S6_PLBW peripheral,
specifying *_ConfigTable is incorrect as it refers to the second instance ...
Is this the design from the co-processing speedway ?
If yes, send me a mail (Mario.Bergeron@avnet.com), I have a 13.1 version ...
02-07-2012 02:22 PM
I finally managed to get a an error free compile. The Demo runs but it hangs after a while in the middle of the printf and gives the following in the terminal:
Reset and Initialize the FMC devices ...
Camera 2 detected.
Detected Video Dimensions = 1280 x 720
Detected Video Resolution = 720P
Video Resolution set to 720P
Clock generator set to 74.25 MHz.
---- Press Any K
I get some image in the monitor but it seems to have sync problems as it appears with horisontal tearing and shaking.
I skipped the FMC Module Validation as proposed in similar topic and in .ucf used the:
NET "fmc_imageov_video_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE; as mentioned earlier in this post.
This is my latest project for EDK 13.1
02-15-2012 03:05 AM
A couple of corrections in the .mhs file but same problem. Microblaze hangs after the "ivk_fb_set_input_resolution( resolution, 1 );" is called.
As the AVNET employees are not responding I kindly request if someone else have managed to run a stable version of the demo in a ML605 board to send me a feedback. I share my current project version.
Any help would be appreciated especially if someone could sent me his own project to check if something else is going wrong.
05-01-2012 04:40 PM - edited 05-01-2012 04:46 PM
I am also using ML605 board and trying to connect the dual image sensor to my FPGA board via FMC module.
I will look into your design and we may try to overcome the problem together.
By the way, have you managed to receive pixels from camera and buffer in BRAM without MicroBlaze?
05-21-2012 04:56 PM
I've been testing the camera based on your system and i don't have the problem you have.
Instead, I have encountered a few problems that you don't....I am wondering if you could possibly give me a hand or some suggestions.
1. The returned RESOLUTION remains 0x0.
I checked the code using ChipScope and found that the PCLK(fmc_imageov_cam1_clk_pin) remains HIGH.
However, when checking using the osciloscope, the following ports are working properly and the PCLK is 47MHz and is stable:
the PCLK pin on the camera, the H4 pin on FMC module and FPGA pin A10 on Xilinx Virtex-6 FPGA board.
(I am using camera 1 instead of camera 2, and I've changed the UCF file accordingly:
Net fmc_imageov_cam1_clk_pin LOC = A10; # FMC1 - H4 (CLK0_M2C_P)
Net fmc_imageov_cam1_pwdn_pin LOC = L30; # FMC1 - C23 (LA18_N_CC)
Net fmc_imageov_cam1_rst_pin LOC = F31; # FMC1 - D8 (LA01_P_CC)
Net fmc_imageov_cam1_frame_valid_pin LOC = K33; # FMC1 - C10 (LA06_P)
Net fmc_imageov_cam1_line_valid_pin LOC = J34; # FMC1 - C11 (LA06_N)
Net fmc_imageov_cam1_data_pin LOC = L26; # FMC1 - D15 (LA09_N)
Net fmc_imageov_cam1_data_pin LOC = L25; # FMC1 - D14 (LA09_P)
Net fmc_imageov_cam1_data_pin LOC = G30; # FMC1 - C15 (LA10_N)
Net fmc_imageov_cam1_data_pin LOC = F30; # FMC1 - C14 (LA10_P)
Net fmc_imageov_cam1_data_pin LOC = H32; # FMC1 - H14 (LA07_N)
Net fmc_imageov_cam1_data_pin LOC = G32; # FMC1 - H13 (LA07_P)
Net fmc_imageov_cam1_data_pin LOC = K29; # FMC1 - G13 (LA08_N)
Net fmc_imageov_cam1_data_pin LOC = J30; # FMC1 - G12 (LA08_P)
Net fmc_imageov_cam1_data_pin LOC = H33; # FMC1 - D12 (LA05_N)
Net fmc_imageov_cam1_data_pin LOC = H34; # FMC1 - D11 (LA05_P)
By the way, the BIT file is generated using ISE instead of EDK, the EDK system is include in the ISE project as a component.
I am not sure if this may be the cause of the problem. But as my EDK always fail to generate BIT file when launched directly, I have to launch it from within ISE and generate the BIT file inside ISE. I think the only difference is that IO buffers are added to ports when generating the BIT file within ISE.
Besides, I also checked PG_C2M.
It says in Spartan®-6 Industrial Video Processing Kit EDK Reference Design Tutorial:
If the camera is detected, but a video resolution of 0 x 0 is detected, it may be possible that the voltage level translators are disabled. This can be caused by PG_C2M not being asserted high.
FMC – pin D1 : PG_C2M => expected to 2.5V
I probed pin D1 and the voltage is 3.3V. Would this cause any problem? Anyway, it is HIGH.
2. Since I don't need all the functions in the demo, I want to keep only three ip cores: the DDR MPMC for data storage, sg_i2c_controller_v6_plbw_0 for SCCB camera configuration, and ivk_video_det_0 for image resolution detection.
However, when I removed some of the ip cores, the I2C failed to program the camera.
Before removing the ip cores, when running the following sentence in SDK, the data on SDA port is : I2C address of I2C_MUX + Control signal (decides which I2C devices to be accessed).
mux_data = 0x0F; // all I2C slaves are selected
num_bytes = pContext->pIIC->fpIicWrite( pContext->pIIC, FMC_IMAGEOV_I2C_MUX_ADDR, mux_data, &mux_data, 1);
After I removed some of the ip cores, the data on SDA is : I2C address of I2C_MUX (no control signal is sent out from FPGA)
So no I2C device can be accessed.
I thought that sg_i2c_controller_v6_plbw_0 is the only ip that is related to the configuration of camera. But it seems that there is another ip that works together with sg_i2c_controller_v6_plbw_0 so as to configure the I2C.
I am wondering which IP it is...
3.The camera starts working when PWDN is set LOW.
After programming the board (but before running SDK), the PWDN is already set LOW and the camera starts working. I am wondering which ip(in EDK) is configuring the camera whenever the FPGA is programmed?
By the way, I am think of ordeing another camera with sensor 0V9215.
I am now using OV9715, however, the actually resolution is 640x400@30fps when displayed in RGB color mode (4pixels actually represent one pixel).
It says on the datasheet of OV9215 that the chroma is B/W but the output format is RAW RGB. I am wondering what is the actually resolution of OV9215.
Does the RAW RGB means that even the chroma is B/W for OV9215, it still requires 4 pixels to represent one pixel with interpolation used?
I am now in need of a camera that is able to work at 640x480@60fps B/W, and the camera should be compatible with the Dual Image Sensor FMC module (I need two cameras for the system), any recommendation?
Thanks for any hint.
I am using Xilinx Virtex-6 FPGA board.
Ovnet Dual Image Sensor FMC Module.
OmniVision camera with OV9715 image sensor.
OS:Windows 7 32bits.
10-24-2012 11:04 PM
Did anyone actually get a successful project built for the ML605? I am trying to get the rev_5 one working posted above, except for some reason I can't even get the fmc_imageov_I2c_controller to communicate. Thanks
10-28-2012 12:57 PM
I am looking at my output image, and I get a lot of screen tearing. It almost looks like some of the frames are offset while others are not. I was reading through some other posts, but I could not really get any insight on this issue, would this be a problem with:
A. Frame Buffering
B. Horizontal Vertical Synchronization
Can someone give me a suggestion on what I can do to fix this? Thanks!