06-28-2011 09:27 AM
Going through the "EDK Tutorial – Adding IP to the Video Processing Pipeline" section of the IVK tutorial, I've stumbled upon a problem. The new version of the Color Filter Array Interpolation (CFA) IP LogiCore (v3.0) automatically connects the clock input of the core to the system clock when using the "Interface Selection : EDK Pcore" option. As a part of the XSVI pipeline, it should however be clocked with video input clock signal. I'm using 13.1 version of the tools, so I don't have the access to the legacy versions of the CFA core. Off the top of my head, I think that under such circumstances, the best solution would be to genrate the IP core with the "transparent" interface, and write some kind of VHDL wrapper for it. Such core, with a correctly formatted MPD file should be visible as a XSVI-compatible peripheral and connecting it with the rest of the image processing pipeline shouldn't be that hard (hopefully). Am I correct? Are there any other options to deal with the issue? Does Avnet have any plans on upgrading the reference designs to be compatible with the most recent version of Xilinx tools?
06-28-2011 10:32 AM
I don't have an ideal response for you, but I can provide two alternatives:
1) a solution archive that contains the CFA core and tutorial design that was generated with 12.2
2) a preliminary 13.1 version of the IVK EDK designs
- I have not verified the tutorial with this version yet, so this may not be usefull to you
- the documentation is not updated for this preliminary version yet
I do plan on releasing an updated version of the IVK EDK designs.
I am unsure wether to release them as the existing PLB-based designs, or upgrade them to AXI-based designs.
06-29-2011 01:44 AM
Since Xilinx seems to be going all-in on AXI, I'd personally prefer the AXI version. I did a quick research among my coworkers and they also prefer AXI for new projects. Could you please give us an approximate release date for the updated reference design?
06-29-2011 07:04 AM
Thanks for the feedback.
I would expect to have the AXI-based designs ready sometime this fall.
In the meantime, here is the solution archive for the current 12.2 PLB-based designs.
File name: IVK_EDK_Demonstrations_12_2_20100921_with_solution.zip
Website link: https://avnet.egnyte.com/h-s/20110629/d62533d4c5e54f77