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Visitor
Posts: 1
Registered: ‎01-02-2014

Decoupling capacitors in the AVNET development boards

Privet Folks,

 

I Hope everyone is fine. Privet is not some sort of a magical spell, It just mean Hello in RUSSIAN.

 

SO my question to the admin in particular and to everyone in general is that as the topic says ample about it "Why did the AVNET not use decoupling capacitors for the SPARTAN based-FPGAs as recommended by XILINX". The recommneded decoupling as given in UG393 are 100, 4.7, 0.47 microFarads ..... where as in your boards you have heavily relied on 0.22 uF ... is that because of the high signal integrity requirements due to the multiGiga Transcivers and PCIe interface .... I am talking in the context of your Spartan 6 LX75T Development Board ...... other boards designed by Atlys and NEXYS have used even smaller values i.e. 10nF, 47nF, 4.7 uF, and 0.47uF ..... a detailed reply will be appreciated ... thank you

 

Best regards 

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New Member
Posts: 1
Registered: ‎08-22-2013

Re: Decoupling capacitors in the AVNET development boards

These Caps are used for noise decoupling.

Xilinx recommended values are applicable if all of the FPGA gates are switched simultaneusly which is not the case in general. 

2ndly Decoup. Caps. effects the SNR of GTP which is enough even with small caps. Recommended values are for Defense Grade SNR of signals.

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