Reply
Highlighted
JJ
Regular Visitor
Posts: 6
Registered: ‎01-26-2011
Accepted Solution

EDK 12.4

Hi everyone,

 

since I need AXI support I'd like to use the provided example designs in the latest EDK.

I was able to get a simple "Hello World" test with the example SoC designs running, but when I try to access the ICC stuff (first read register access) the SW hangs.

Did I miss some magic function enabling the FMC card or such?

 

Was anybody able to get examples running on 12.4?

 

Thx&BR,

JJ

 

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: EDK 12.4

The I2C communication is handled with the fmc_iic_sw (1.03.a) library, which is included with the 12.2 reference designs.

 

This library was tested with version 1.16.a of the the Xilinx "iic" driver.

 

Have you changeed/updated the version of the "iic" driver ?

If yes, try to revert it back (in the .mss file) and see if that solves the issue.

 

Regards,

 

Mario.

JJ
Regular Visitor
Posts: 6
Registered: ‎01-26-2011

Re: EDK 12.4

Thanks Mario,

 

switching to the old driver did indeed solve the issue.

So I'm one step further, now the base platform sw works ...

 

... but when I try to compile the Camera Frame Buffer Demo (the one I'd need as template), I run into several new issues.

 

- The SDK microblaze_0 library seems to be a bit incomplete. The xc_iface_t and xc_create commands - used in the processing menu - are not available. Did I miss an option when generating platform spec or support package?

 

- Furthermore, when removing the processing menu from the Frame Buffer Dome, the fmc_imageov_wait_usec function leads to an endless loop (val-- doesn't decrease val in the delay loop).

 

- When bypassing the delays & stepping from line to line where a delay is required (which should lead to sufficient delay Smiley Wink I end up with "Error: Camera not found."

 

BR,JJ

 

 

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: EDK 12.4

JJ,

 

The xc_* functions are related to the drivers created with the pcores that were generated from System Generator.

 

Make sure you have included the following drivers in the SDK library:

 

These are needed by the processing menu

   - sg_spc_s6_plbw

   - sg_bc_s6_plbw

   - sg_cfa_s6_plbw

   - sg_cc_s6_plbw

   - sg_stats_s6_plbw

   - sg_gamma_s6_plbw

 

This one is needed to communicate with the camera:

   - sg_i2c_controller_s6_plbw

Make sure you are using this alternate I2C controller for the fmc_imageov_i2c_scl/sda pins.

I was not able to make the xilinx xps_iic pcore work with the omnivision image sensor.

 

 

Regards,

 

Mario.

JJ
Regular Visitor
Posts: 6
Registered: ‎01-26-2011

Re: EDK 12.4

Hello again Mario,

 

something weird happend here ... the drivers are present in the system.mms of XPS (I can also access the driver docs & MDD right clicking the IP instance), but are replaced with generic drivers in the exported/imported SDK environment.

 

Do you have any idea what could have gone wrong here or how to fix this?

 

Thx&BR,

JJ

 

p.s.: The OV i2c signals seem to be connected propperly.

JJ
Regular Visitor
Posts: 6
Registered: ‎01-26-2011

Re: EDK 12.4

Hi Mario,

 

short update: I was able to select the propper drivers after adding the IVK_Repository also in SDK (Xilinx Tools -> Reosutires ).

Also the Camera Framebuffer demo compiles smooth now ... but the issue with the delay funciton remains.

 

Any idea what still goes wrong?

I saw you used no DDR memory in the original linker script ... are there issues when code/data is put there (overwriting camera data or such)?

 

BR

Juergen

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: EDK 12.4

Juergen,

 

------------------------------------------------------------------------------------

 

I'm not sure what could be causing the delay function to hang ... what happens if you comment it out ?

 

------------------------------------------------------------------------------------

 

You are correct that there are linker scripts in the EDK projects.

You are also correct that these linker scripts define everything in internal BRAM.

 

However, they are not used by the EDK projects.

Sorry about not cleaning them out, which has caused confusion.

 

Look at the .XPS file of the original EDK project to see the memory being used.

All the code/data is placed in external DDR3 memory.

 

The DDR3 memory starts at address 0x10000000.

   The video frame buffers are stored at the start of this region (details in ivk_frame_buffer.c).

   The code/data is stored at address 0x17000000.

This prevents the code/data from colliding with the video frame buffers.

 

 

Regards,

 

Mario.

JJ
Regular Visitor
Posts: 6
Registered: ‎01-26-2011

Re: EDK 12.4

Hi Mario,

 

I think I've found the root cause of the weird behavior in my system ... although I don't know how to fix it Smiley Sad

 

It seems that the DDR-Mem isn't working properly at all ... 

 - If I used DDR only the whole system crashes

 - Dependent of how I mix DDR with Block-RAM (Heap, Code, Instruction) I experience different weird behavior (like the neverending delay)

 

I don't know what's going wrong here, the HW (mhs) as well as the SW are nearly like in your example. DDR itself works fine in simple "Hello World" systems.

Were you able to export one of your more complex environments to 12.4 and if so is it possible for you to share it?

 

Thx&BR

Juergen

 

p.s.: Of course I also took care now that video & other data regions don't overlap.

JJ
Regular Visitor
Posts: 6
Registered: ‎01-26-2011

Re: EDK 12.4

Hi Mario,

 

the issue is solved, I just didn't use the latest bit-files.

So basicly switching to the old i2c drivers and setting up a proper linker script helped.

 

Thx for your support!

 

BR

Juergen

mkr
Regular Visitor
Posts: 7
Registered: ‎11-17-2009

Re: EDK 12.4

In case anyone wondered - the described procedure is also valid for migration to 13.1 version of Xilinx tools. All ipcores can be safely upgraded, but the xps_iic driver needs to be changed from  iic_v2_02_a to iic_v1_16_a in the *.mss file of the project. 

I have one question though - why doesn't the Avnet IP core work with the newest Xilinx drivers? Are there any plans to upgrade the IP core to be compatible with more recent Xilinx software? Version 1.16.a of the IIC driver seems to be the oldest available in 13.1, and I'm worried that with the introduction of future upgrades i won't be able to run the reference designs Avnet provided.