Reply
Highlighted
Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009
Accepted Solution

FMC-DVI DVI Input clock not mapped to global clock input pin

[ Edited ]

The DVI input clock on the FMC-DVI module is mapped to LA07_CC_P (which is a clock capable pin).

   On the S6-LX150T Rev.A, this was mapped to a GCLK input pin on FMC slot #2.

   On the S6-LX150T Rev.B & Rev.C, however, this is no longer mapped to a GCLK input pin on FMC slot #2.

 

This will result in the following error when attempting to build a design using the FMC-DVI module's DVI input clock on FMC slot #2:

 

ERROR: Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock    IOB / BUFGMUX site pair.

 

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: FMC-DVI DVI Input clock not mapped to global clock input pin

[ Edited ]

There are two ways to address this issue:

   1) Add a "CLOCK_DEDICATED_ROUTE = FALSE" constraint and adjust in TFP403 device via I2C

       => this is what has been done in the following two reference designs:

            - EDK and System Generator Designs - DVI/Camera Video Processing and Frame Buffer Demos

            - HDL Designs - DVI Pass-Through Demo

   2) Place FMC-DVI module on FMC slot #1, sinceLA07_CC_P is mapped to a GCLK input pin on FMC slot #1

 

1) Add a "CLOCK_DEDICATED_ROUTE = FALSE" constraint and adjust in TFP403 device via I2C

 

I have been able to workaround this by using a "CLOCK_DEDICATED_ROUTE=FALSE" constraint, as follows:

   # The FMC-DVI's DVI input clock pin is not on a dedicated clock input
   # - keep the following constraints to ensure proper functionnality
   NET fmc_dvidp_dvii_clk_pin CLOCK_DEDICATED_ROUTE = FALSE;
   INST "clock_generator_1*PLL_ADV_inst" LOC = PLL_ADV_X0Y0;

 

I also fixed the PLL_ADV to location X0Y0, to keep results somewhat deterministic.  You can do the same, if you are using one.

 

I also set the TFP403 device's OCK_INVERTED setting via I2C to adjust the clock/data timing to compensate for the "non optimal" IOB/BUFGMUX route.

 

This solution has been working for me in the DVI reference designs from VGA (pixel rate = 25MHz) to UXGA (pixel rate = 150MHz).

 

 

2) Place FMC-DVI module on FMC slot #1, sinceLA07_CC_P is mapped to a GCLK input pin on FMC slot #1

 

I recommend solution 1), it has been working for me.

If this solution is not acceptable to your customer, they can move the FMC-DVI module to FMC slot #1,

where LA07_CC_P has been mapped to a GCLK input pin.

 

 

Regards,

 

Mario.

Regular Visitor
Posts: 4
Registered: ‎03-21-2012

Re: FMC-DVI DVI Input clock not mapped to global clock input pin

I'm also using a S6-LX150T with the FMC-DVI board. I believe I have S6-LX150T Rev. E. I need to put the FMC-DVI on FMC #1, but I'm a bit confused as to what would need to change from the reference video pass through design. I've used the master UCF for the S6-LX150T Rev. C to remap the dvi inputs/outputs from FMC #2 to FMC #1 in the system.ucf and it's _almost_ correct. The problem seems to be that some pixel values are not right. The output video (pass through -- unaltered) has green and red pixels where the color should be white (or close to white), such as on edges of tables, etc. Everything else works correctly. I suspect this is from incorrect ucf remapping (being that I'm on revision E and the only master UCF available is revsion C). But perhaps something needs to change in the Picoblaze IIC config as well? Any suggestions would be most appreciated.

 

Thanks,
Matt 

Regular Visitor
Posts: 4
Registered: ‎03-21-2012

Re: FMC-DVI DVI Input clock not mapped to global clock input pin

Update:

 

I've been informed that there is no revision E of this board. So I'm assuming I have D (as I just ordered it from AVNet). Regardless, I've triple checked the UCF mapping and compared it against the board schematic. The mapping of FMC2 to FMC1 pins appears to be correct/accurate. Below is my ucf. It's basically the fmc_dvidp_dvi_passthrough_demo_s6ivk.ucf with another set of pins pulled in for FMC1 for the additional FMC-DVI I have attached. 

 

Again, the problem seems to be that a video signal pass through on FMC2 displays correctly, but the same signal coming through FMC1 displays bad pixels on highly bright areas (almost as if it's over flowing). The only changes I've done to the pass through code are to instantiate a duplicate set of modules to handle the duplicate set of inputs from FMC1.

 

##############################################################################
# Clock & Reset Input
##############################################################################

## Clock constraints
NET  clk_100mhz  LOC = U23  | IOSTANDARD = LVCMOS25;

Net clk_100mhz TNM_NET = sys_clk;
TIMESPEC TS_sys_clk = PERIOD sys_clk 10000 ps;


## Reset constraints
#Net reset TIG;
#Net reset LOC= M19 | IOSTANDARD = LVCMOS15;


###########################################
# Push-buttons
###########################################
Net push_buttons[0]  LOC = M19 | IOSTANDARD = LVCMOS25;
Net push_buttons[1]  LOC = L20 | IOSTANDARD = LVCMOS25;
Net push_buttons[2]  LOC = L21 | IOSTANDARD = LVCMOS25;
Net push_buttons[3]  LOC = H20 | IOSTANDARD = LVCMOS25;

###########################################
# FMC
###########################################
#NET fmc_ipmi_i2c_scl		LOC = AB3 | SLEW = SLOW | TIG | IOSTANDARD = LVCMOS33;
#NET fmc_ipmi_i2c_sda		LOC = AB1 | SLEW = SLOW | TIG | IOSTANDARD = LVCMOS33;


###########################################
# FMC-DVIDP - I2C
###########################################
Net fmc2_dvidp_i2c_scl LOC = AB21 | SLEW = SLOW | TIG | PULLUP; # FMC2 - D15 (LA09_N)
Net fmc2_dvidp_i2c_sda LOC = AA21 | SLEW = SLOW | TIG | PULLUP; # FMC2 - D14 (LA09_P)
Net fmc2_dvidp_i2c_rst LOC =  W17; # FMC2 - G15 (LA12_P)

Net fmc1_dvidp_i2c_scl LOC = E16 | SLEW = SLOW | TIG | PULLUP; # FMC1 - D15 (LA09_N)
Net fmc1_dvidp_i2c_sda LOC = F16 | SLEW = SLOW | TIG | PULLUP; # FMC1 - D14 (LA09_P)
Net fmc1_dvidp_i2c_rst LOC =  B23; # FMC1 - G15 (LA12_P)


###########################################
# FMC-DVIDP - DVI Input
###########################################
Net fmc2_dvidp_dvii_clk          LOC = W14; # FMC2 - D20 (LA17_P_CC)
TIMESPEC TS_fmc2_dvidp_dvii_clk = PERIOD fmc2_dvidp_dvii_clk 6.0 ns; # 162 MHz
#TIMESPEC TS_fmc2_dvidp_dvii_clk = PERIOD fmc2_dvidp_dvii_clk 15.0 ns; # 162 MHz
NET fmc2_dvidp_dvii_clk          CLOCK_DEDICATED_ROUTE = FALSE;
Net fmc2_dvidp_dvii_de           LOC = Y16; # FMC2 - C15 (LA10_N)
Net fmc2_dvidp_dvii_vsync        LOC = W18; # FMC2 - G16 (LA12_N)
Net fmc2_dvidp_dvii_hsync        LOC = U13; # FMC2 - H16 (LA11_P)
Net fmc2_dvidp_dvii_blue[0]      LOC = V23; # FMC2 - G27 (LA25_P)
Net fmc2_dvidp_dvii_blue[1]      LOC = R26; # FMC2 - H26 (LA21_N)
Net fmc2_dvidp_dvii_blue[2]      LOC =AE25; # FMC2 - D26 (LA26_P)
Net fmc2_dvidp_dvii_blue[3]      LOC = Y24; # FMC2 - C26 (LA27_P)
Net fmc2_dvidp_dvii_blue[4]      LOC = Y11; # FMC2 - D24 (LA23_N)
Net fmc2_dvidp_dvii_blue[5]      LOC = T20; # FMC2 - G25 (LA22_N)
Net fmc2_dvidp_dvii_blue[6]      LOC = T19; # FMC2 - G24 (LA22_P)
Net fmc2_dvidp_dvii_blue[7]      LOC = U24; # FMC2 - H25 (LA21_P)
Net fmc2_dvidp_dvii_green[0]     LOC = Y17; # FMC2 - H23 (LA19_N)
Net fmc2_dvidp_dvii_green[1]     LOC = AC5; # FMC2 - D23 (LA23_P)
Net fmc2_dvidp_dvii_green[2]     LOC = U25; # FMC2 - C22 (LA18_P_CC)
Net fmc2_dvidp_dvii_green[3]     LOC = Y13; # FMC2 - D21 (LA17_N_CC)
Net fmc2_dvidp_dvii_green[4]     LOC =AC23; # FMC2 - G22 (LA20_N)
Net fmc2_dvidp_dvii_green[5]     LOC =AA17; # FMC2 - G21 (LA20_P)
Net fmc2_dvidp_dvii_green[6]     LOC = W20; # FMC2 - H22 (LA19_P)
Net fmc2_dvidp_dvii_green[7]     LOC = V16; # FMC2 - H20 (LA15_N)
Net fmc2_dvidp_dvii_red[0]       LOC = U15; # FMC2 - H19 (LA15_P)
Net fmc2_dvidp_dvii_red[1]       LOC = AA6; # FMC2 - G19 (LA16_N)
Net fmc2_dvidp_dvii_red[2]       LOC =AA16; # FMC2 - C19 (LA14_N)
Net fmc2_dvidp_dvii_red[3]       LOC = Y15; # FMC2 - C18 (LA14_P)
Net fmc2_dvidp_dvii_red[4]       LOC =AB15; # FMC2 - D18 (LA13_N)
Net fmc2_dvidp_dvii_red[5]       LOC = AA7; # FMC2 - G18 (LA16_P)
Net fmc2_dvidp_dvii_red[6]       LOC = V13; # FMC2 - H17 (LA11_N)
Net fmc2_dvidp_dvii_red[7]       LOC =AA15; # FMC2 - D17 (LA13_P)

Net fmc1_dvidp_dvii_clk          LOC = B12; # FMC2 - D20 (LA17_P_CC)
TIMESPEC TS_fmc1_dvidp_dvii_clk = PERIOD fmc1_dvidp_dvii_clk 6.0 ns; # 162 MHz
#TIMESPEC TS_fmc1_dvidp_dvii_clk = PERIOD fmc1_dvidp_dvii_clk 15.0 ns; # 162 MHz
NET fmc1_dvidp_dvii_clk          CLOCK_DEDICATED_ROUTE = FALSE;
Net fmc1_dvidp_dvii_de           LOC = D22; # FMC2 - C15 (LA10_N)
Net fmc1_dvidp_dvii_vsync        LOC = A23; # FMC2 - G16 (LA12_N)
Net fmc1_dvidp_dvii_hsync        LOC = B22; # FMC2 - H16 (LA11_P)
Net fmc1_dvidp_dvii_blue[0]      LOC = F9; # FMC2 - G27 (LA25_P)
Net fmc1_dvidp_dvii_blue[1]      LOC = G8; # FMC2 - H26 (LA21_N)
Net fmc1_dvidp_dvii_blue[2]      LOC = F10; # FMC2 - D26 (LA26_P)
Net fmc1_dvidp_dvii_blue[3]      LOC = G12; # FMC2 - C26 (LA27_P)
Net fmc1_dvidp_dvii_blue[4]      LOC = G11; # FMC2 - D24 (LA23_N)
Net fmc1_dvidp_dvii_blue[5]      LOC = G9; # FMC2 - G25 (LA22_N)
Net fmc1_dvidp_dvii_blue[6]      LOC = H9; # FMC2 - G24 (LA22_P)
Net fmc1_dvidp_dvii_blue[7]      LOC = H8; # FMC2 - H25 (LA21_P)
Net fmc1_dvidp_dvii_green[0]     LOC = G10; # FMC2 - H23 (LA19_N)
Net fmc1_dvidp_dvii_green[1]     LOC = J11; # FMC2 - D23 (LA23_P)
Net fmc1_dvidp_dvii_green[2]     LOC = J13; # FMC2 - C22 (LA18_P_CC)
Net fmc1_dvidp_dvii_green[3]     LOC = A12; # FMC2 - D21 (LA17_N_CC)
Net fmc1_dvidp_dvii_green[4]     LOC = E12; # FMC2 - G22 (LA20_N)
Net fmc1_dvidp_dvii_green[5]     LOC = F12; # FMC2 - G21 (LA20_P)
Net fmc1_dvidp_dvii_green[6]     LOC = H10; # FMC2 - H22 (LA19_P)
Net fmc1_dvidp_dvii_green[7]     LOC = G13; # FMC2 - H20 (LA15_N)
Net fmc1_dvidp_dvii_red[0]       LOC = H12; # FMC2 - H19 (LA15_P)
Net fmc1_dvidp_dvii_red[1]       LOC = J17; # FMC2 - G19 (LA16_N)
Net fmc1_dvidp_dvii_red[2]       LOC = E14; # FMC2 - C19 (LA14_N)
Net fmc1_dvidp_dvii_red[3]       LOC = F14; # FMC2 - C18 (LA14_P)
Net fmc1_dvidp_dvii_red[4]       LOC = B21; # FMC2 - D18 (LA13_N)
Net fmc1_dvidp_dvii_red[5]       LOC = J16; # FMC2 - G18 (LA16_P)
Net fmc1_dvidp_dvii_red[6]       LOC = A22; # FMC2 - H17 (LA11_N)
Net fmc1_dvidp_dvii_red[7]       LOC = C21; # FMC2 - D17 (LA13_P)

###########################################
# FMC-DVIDP - DVI Output
###########################################
Net fmc2_dvidp_dvio_clk          LOC = U26; # FMC2 - C23 (LA18_N_CC)
Net fmc2_dvidp_dvio_reset_n      LOC = U20; # FMC2 - G37 (LA33_N)
Net fmc2_dvidp_dvio_de           LOC = T23; # FMC2 - H35 (LA30_N)
Net fmc2_dvidp_dvio_vsync        LOC = U19; # FMC2 - G36 (LA33_P)
Net fmc2_dvidp_dvio_hsync        LOC = U21; # FMC2 - H37 (LA32_P)
Net fmc2_dvidp_dvio_data[0]      LOC =AD26; # FMC2 - G34 (LA31_N)
Net fmc2_dvidp_dvio_data[1]      LOC =AD24; # FMC2 - G33 (LA31_P)
Net fmc2_dvidp_dvio_data[2]      LOC = T22; # FMC2 - H34 (LA30_P)
Net fmc2_dvidp_dvio_data[3]      LOC =AC26; # FMC2 - H32 (LA28_N)
Net fmc2_dvidp_dvio_data[4]      LOC =AA24; # FMC2 - G31 (LA29_N)
Net fmc2_dvidp_dvio_data[5]      LOC =AA23; # FMC2 - G30 (LA29_P)
Net fmc2_dvidp_dvio_data[6]      LOC =AC25; # FMC2 - H31 (LA28_P)
Net fmc2_dvidp_dvio_data[7]      LOC =AB26; # FMC2 - H29 (LA24_N)
Net fmc2_dvidp_dvio_data[8]      LOC =AB24; # FMC2 - H28 (LA24_P)
Net fmc2_dvidp_dvio_data[9]      LOC = W24; # FMC2 - G28 (LA25_N)
Net fmc2_dvidp_dvio_data[10]     LOC = Y26; # FMC2 - C27 (LA27_N)
Net fmc2_dvidp_dvio_data[11]     LOC =AE26; # FMC2 - D27 (LA26_N)

Net fmc1_dvidp_dvio_clk          LOC = H13; # FMC2 - C23 (LA18_N_CC)
Net fmc1_dvidp_dvio_reset_n      LOC = B3; # FMC2 - G37 (LA33_N)
Net fmc1_dvidp_dvio_de           LOC = A4; # FMC2 - H35 (LA30_N)
Net fmc1_dvidp_dvio_vsync        LOC = C3; # FMC2 - G36 (LA33_P)
Net fmc1_dvidp_dvio_hsync        LOC = A3; # FMC2 - H37 (LA32_P)
Net fmc1_dvidp_dvio_data[0]      LOC = A5; # FMC2 - G34 (LA31_N)
Net fmc1_dvidp_dvio_data[1]      LOC = B5; # FMC2 - G33 (LA31_P)
Net fmc1_dvidp_dvio_data[2]      LOC = B4; # FMC2 - H34 (LA30_P)
Net fmc1_dvidp_dvio_data[3]      LOC = C5; # FMC2 - H32 (LA28_N)
Net fmc1_dvidp_dvio_data[4]      LOC = F5; # FMC2 - G31 (LA29_N)
Net fmc1_dvidp_dvio_data[5]      LOC = G6; # FMC2 - G30 (LA29_P)
Net fmc1_dvidp_dvio_data[6]      LOC = D5; # FMC2 - H31 (LA28_P)
Net fmc1_dvidp_dvio_data[7]      LOC = F6; # FMC2 - H29 (LA24_N)
Net fmc1_dvidp_dvio_data[8]      LOC = F7; # FMC2 - H28 (LA24_P)
Net fmc1_dvidp_dvio_data[9]      LOC = E8; # FMC2 - G28 (LA25_N)
Net fmc1_dvidp_dvio_data[10]     LOC = F11; # FMC2 - C27 (LA27_N)
Net fmc1_dvidp_dvio_data[11]     LOC = E10; # FMC2 - D27 (LA26_N)

###########################################
# FMC-DVIDP - Test Points
###########################################
Net fmc1_dvidp_tp1 LOC = Y12 | TIG; # FMC2 - D11 (LA05_P)
Net fmc1_dvidp_tp2 LOC =AA12 | TIG; # FMC2 - D12 (LA05_N)
Net fmc1_dvidp_tp3 LOC = W16 | TIG; # FMC2 - C14 (LA10_P)

Net fmc2_dvidp_tp1 LOC = F20 | TIG; # FMC2 - D11 (LA05_P)
Net fmc2_dvidp_tp2 LOC = E20 | TIG; # FMC2 - D12 (LA05_N)
Net fmc2_dvidp_tp3 LOC = D21 | TIG; # FMC2 - C14 (LA10_P)