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Regular Visitor
Posts: 3
Registered: ‎02-08-2013

Problem: Import IVK_Camera_Frame_Buffer_Demo to ISe

Hi.

What i need to use project from EDK in ISE project?

Instance of EDK project is ready in itself?

I map only clk input from top file, synthesize is fine. I have error in Map:

 

ERRORSmiley TonguehysDesignRules:1461 - Incomplete PLL_ADV configuration. The signal
Inst_system/clock_generator_1/clock_generator_1/SIG_PLL0_CLKFBOUT on the CLKFBIN pin of PLL_ADV comp
Inst_system/clock_generator_1/clock_generator_1/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst is driven by the PLL_ADV
CLKFBOUT pin therefore the COMPENSATION attribute must be set INTERNAL, DCM2PLL, or PLL2DCM.
ERRORSmiley TonguehysDesignRules:1461 - Incomplete PLL_ADV configuration. The signal
Inst_system/clock_generator_0/clock_generator_0/SIG_PLL0_CLKFBOUT on the CLKFBIN pin of PLL_ADV comp
Inst_system/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst is driven by the PLL_ADV
CLKFBOUT pin therefore the COMPENSATION attribute must be set INTERNAL, DCM2PLL, or PLL2DCM.
ERRORSmiley TonguehysDesignRules:1461 - Incomplete PLL_ADV configuration. The signal
Inst_system/clock_generator_0/clock_generator_0/SIG_PLL1_CLKFBOUT on the CLKFBIN pin of PLL_ADV comp
Inst_system/clock_generator_0/clock_generator_0/PLL1_INST/Using_PLL_ADV.PLL_ADV_inst is driven by the PLL_ADV
CLKFBOUT pin therefore the COMPENSATION attribute must be set INTERNAL, DCM2PLL, or PLL2DCM.
ERRORSmiley Tongueack:1642 - Errors in physical DRC.

 

Please help me. 

Jack.

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: Problem: Import IVK_Camera_Frame_Buffer_Demo to ISe

[ Edited ]

Jack,

 

It looks like the tool does not like the clock_generator_1 PCORE instance, which is used for the video clock input from the FMC module.

 

Can you try to remove it from the EDK sub-system ?

 

Change this line:

   PORT fmc_imageov_video_clk_pin = fmc_imageov_video_clk, DIR = I, SIGIS = CLK, CLK_FREQ = 74250000

to

   PORT fmc_imageov_video_clk_pin = display_clk, DIR = I, SIGIS = CLK, CLK_FREQ = 74250000

 

And comment out the clock_generator_1 instance:

   #BEGIN clock_generator
   #   PARAMETER INSTANCE = clock_generator_1

   #   ...
   #   PORT CLKIN = fmc_imageov_video_clk
   #   PORT CLKOUT0 = display_clk

   #   ...
   #END

 

 

Regards,

 

Mario.

Regular Visitor
Posts: 3
Registered: ‎02-08-2013

Re: Problem: Import IVK_Camera_Frame_Buffer_Demo to ISe

Thank you for replay.

Now We have problem with dmc_0_rst in PORT Gpo:

BEGIN xps_iic
PARAMETER INSTANCE = xps_iic_0
PARAMETER HW_VER = 2.03.a
PARAMETER C_GPO_WIDTH = 3
PARAMETER C_BASEADDR = 0x81620000
PARAMETER C_HIGHADDR = 0x8162ffff
BUS_INTERFACE SPLB = mb_plb
PORT Scl = xps_iic_0_Scl
PORT Sda = xps_iic_0_Sda
PORT Gpo = dcm_0_rst & 0b0 & fmc1_enable
END

dcm_0_rst is comment in clock_generator_1...

Which reset i can replace dcm_0_rst? 

 

Regards,

Jack.

 

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: Problem: Import IVK_Camera_Frame_Buffer_Demo to ISe

Jack,

 

The dcm_rst_0 signal was driving the reset port on the clock_generator_1.

Now that it's gone, it is no longer needed in the EDK sub-system.

 

Please replace the following line:

   PORT Gpo = dcm_0_rst & 0b0 & fmc1_enable

with the following

   PORT Gpo = 0b0 & 0b0 & fmc1_enable

 

Regards,

 

Mario.

Regular Visitor
Posts: 3
Registered: ‎02-08-2013

Re: Problem: Import IVK_Camera_Frame_Buffer_Demo to ISe

[ Edited ]

Thakns for your replay.

I have still problem with clock_generator_0 

 

 

ERRORSmiley TonguehysDesignRules:1461 - Incomplete PLL_ADV configuration. The signal
Inst_system/clock_generator_0/clock_generator_0/SIG_PLL0_CLKFBOUT on the CLKFBIN pin of PLL_ADV comp
Inst_system/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst is driven by the PLL_ADV
CLKFBOUT pin therefore the COMPENSATION attribute must be set INTERNAL, DCM2PLL, or PLL2DCM.
ERRORSmiley Tongueack:1642 - Errors in physical DRC.

 

I found the warnings and dont understand their

WARNING:MapLib:830 - Cannot automatically set COMPENSATION attribute for PLL_ADV
Inst_system/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_A
DV_inst because no input clock signal was found.
WARNING:MapLib:701 - Signal clk connected to top level port clk has been
removed.

 

Im not sure if my ISE project is correct.

I have subsystem maped only with declared signal. In system i have only clk input and fmc_imageov_dvi_data_pin connected to output. I want to check how to connect EDK projekt to ISE. 

 

Regards

Jack.

Regular Visitor
Posts: 8
Registered: ‎11-28-2013

Re: Problem: Import IVK_Camera_Frame_Buffer_Demo to ISe

Hi Dear Jack

 

I have same issue. I just wondering that have you manage to finish your code? If yeas is there any chance to share it in the community please.

 

Regards

 

Saeed