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Regular Visitor
Posts: 9
Registered: ‎06-24-2010
Accepted Solution

VFBC_FIFO_RDWD

Hello,

I need your help in order

to correctly manage the vfbc video fifo data  in the mpmc core.

In particular, I'm trying to develop

a pcore that concurrently  read and writes data from a single vfbc port.

I suppose that, since there are two separate data interfaces on the vfbc port, 

there is also a separate data fifo on each interface.

 

The problem is that when I active both the vfbc_rd_read and  vfbc_wd_write

signals, the  vfbc_wd_full signal becomes high even if I've only written half data in the  "wd fifo".

(at C_VFBC_RDWD_FIFO_DEPTH/2).

 

Maybe there is a just single fifo data on each vfbc port?

 

Thank you in advance,

Giovanni

 

 

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: VFBC_FIFO_RDWD

Giovanni,

 

There is a seperate FIFO for each of the read and write ports.

The length of the FIFO is configurable via the PCORE parameters.

 

Be aware that there is one command port per VFBC, and the command port will service one command at a time.

If you are receiving and sending an image at the same time, you cannot issue a frame read command and a frame write command since the first one received will starve the other.

 

The way to do this is to break the frame transfer command into seperate line transfer commands. 

In this way, the line reads and line writes will be interleaved. 

One may starve the other, but only during a line transfer.

As long as the FIFOs are long enough, this will work.

 

Regards,

 

Mario.

Regular Visitor
Posts: 9
Registered: ‎06-24-2010

Re: VFBC_FIFO_RDWD

Thank you Mario,

it finally works.

 

Your help is always precious.

Regards,

Giovanni

Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: VFBC_FIFO_RDWD

Giovanni,

 

That's great news !

 

Regards,

 

Mario.