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Regular Visitor
Posts: 9
Registered: ‎12-01-2011

IIC screws up dual CPU design

I design a dual PLB based Microblaze system built on AVNET S6LX150 development board

The design includes shared DDR2 memory, soft TEMAC, FLASH and RS232. The system is built and functions well until I add the last element , the IIC interface.  At this point EDK is unable to implement the design always ending up with the same  error message  

 

ERROR:Xflow - Program par returned error code 30. Aborting flow execution...

make: *** [__xps/mbx2_system_routed] Error 1

 

I tried a dozen of times slightly changing configuration. It is all the same.

Going through the messages I found that 1 signal is unrouted

 

Unroutable          signal: Dcm_all_locked                 pin:  MCB_DDR3/MCB_DDR3/mpmc_core_0/gen_spartan6_mcb.gen_spartan6_bufpll_mcb.bufpll_0/LOCKED

 

The relationship between IIC and mpmc is not obvious. I am puzzled. This is definitely not a resource problem. FPGA is large and the design uses a tiny  fraction of it.

Does anyone have any ideas.

Thanks

PS. IIC works fine in a single CPU design

mbx2_assembly.jpg
Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: IIC screws up dual CPU design

I have seen this error message in the past. Although it's been a few years, but I believe I got around it by lowering the frequency of the system clock.

Regular Visitor
Posts: 9
Registered: ‎12-01-2011

Re: IIC screws up dual CPU design

Thank you for reply. It is always nice to see that Avnet cares about user problems. I tried 62.5MHz, the lowest I am allowed with my configuration.

Still the same error message. I tried EDK 13.3 and 14.5. All the same. As I mentioned in my original post the system is  implemented without errors

if I remove IIC interface from the design. As I understand IIC doesn't connect directly to the clock generator, possibly indirectly via the system bus.

So the connection between IIC and the problem of routing Dcm_all_locked signal is not obvious.

Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: IIC screws up dual CPU design

Just for debugging purposes, would you set  the clock to 50MHz to see if it will route.

Regular Visitor
Posts: 9
Registered: ‎12-01-2011

Re: IIC screws up dual CPU design

The design contains Soft_TEMAC. I am getting error with 50MHz clock

 

Component <Soft_TEMAC> has no valid clock configuration with the current clock settings of the system

 

The smallest frequency that works is 62.5MHz

 

 

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Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: IIC screws up dual CPU design

Unfortunately, the initial Dcm_all_locked error message that you are getting is one of the worst error messages I've ever seen. It's basically useless and doesn't assist you in getting to the root cause of the problem. If you don't mind, would you please open a web case for this on the Xilinx support web site: http://www.xilinx.com/support/clearexpress/websupport.htm.

 

Thanks.