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Visitor
Posts: 7
Registered: ‎09-07-2014
Accepted Solution

Mapping step does not work in my kit

Hi all.
I purchased an Avnet Spartan-6 LX150T kit. It included a CD with an ISE Suite version 12. First time I tryed a new design a message error arose saying that Mapping was not available for that device. I was instructed by friends to download a newer version of ISE suíte which I did. I installed version 14.7 but the problem still remains. Can someone, please, tell me what I need to do in order to run an application in the kit I bought? During compilation it always stops in the Mapping step.
Thanks so much.
Joao

Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: Mapping step does not work in my kit

Would you please send me your log file so that I can see the complete error message? I'm assuming you have correctly installed the license file.

Visitor
Posts: 7
Registered: ‎09-07-2014

Re: Mapping step does not work in my kit

Hi.

Thanks for the support. The console messages are below. As for the licence.lic I simply followed the steps which are not so complicated. If you wish I can send the licence.lic file too.

Thanks again

 

 

 

Started : "Synthesize - XST".

Running xst...

Command Line: xst -intstyle ise -ifn "C:/Documents and Settings/JCR/Test_LEDs/test_LED.xst" -ofn "C:/Documents and Settings/JCR/Test_LEDs/test_LED.syr"

Reading design: test_LED.prj

 

=========================================================================

*                         HDL Parsing                                 *

=========================================================================

Parsing VHDL file "C:\Documents and Settings\JCR\Test_LEDs\test_LED.vhd" into library work

Parsing entity <test_LED>.

Parsing architecture <Behavioral> of entity <test_led>.

 

=========================================================================

*                           HDL Elaboration                           *

=========================================================================

 

Elaborating entity <test_LED> (architecture <Behavioral>) from library <work>.

 

=========================================================================

*                           HDL Synthesis                               *

=========================================================================

 

Synthesizing Unit <test_LED>.

   Related source file is "C:\Documents and Settings\JCR\Test_LEDs\test_LED.vhd".

   Summary:

            no macro.

Unit <test_LED> synthesized.

 

=========================================================================

HDL Synthesis Report

 

Found no macro

=========================================================================

 

=========================================================================

*                       Advanced HDL Synthesis                         *

=========================================================================

 

 

=========================================================================

Advanced HDL Synthesis Report

 

Found no macro

=========================================================================

 

=========================================================================

*                        Low Level Synthesis                           *

=========================================================================

 

Optimizing unit <test_LED> ...

 

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block test_LED, actual ratio is 0.

 

Final Macro Processing ...

 

=========================================================================

Final Register Report

 

Found no macro

=========================================================================

 

=========================================================================

*                           Partition Report                           *

=========================================================================

 

Partition Implementation Status

-------------------------------

 

No Partitions were found in this design.

 

-------------------------------

 

=========================================================================

*                           Design Summary                             *

=========================================================================

 

Clock Information:

------------------

No clock signals found in this design

 

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

 

Timing Summary:

---------------

Speed Grade: -3

 

   Minimum period: No path found

   Minimum input arrival time before clock: No path found

   Maximum output required time after clock: No path found

   Maximum combinational path delay: 4.372ns

 

=========================================================================

 

Process "Synthesize - XST" completed successfully

 

Started : "Translate".

Running ngdbuild...

Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc Test_LEDs.ucf -p xc6slx150t-fgg676-3 "test_LED.ngc" test_LED.ngd

 

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle

ise -dd _ngo -nt timestamp -uc Test_LEDs.ucf -p xc6slx150t-fgg676-3 test_LED.ngc

test_LED.ngd

 

Reading NGO file "C:/Documents and Settings/JCR/Test_LEDs/test_LED.ngc" ...

Gathering constraint information from source properties...

 

Annotating constraints to design from ucf file "Test_LEDs.ucf" ...

Resolving constraint associations...

Checking Constraint Associations...

Done...

 

Checking expanded design ...

 

Partition Implementation Status

-------------------------------

 

No Partitions were found in this design.

 

-------------------------------

 

NGDBUILD Design Results Summary:

Number of errors:     0

Number of warnings:   0

 

Writing NGD file "test_LED.ngd" ...

Total REAL time to NGDBUILD completion: 9 sec

Total CPU time to NGDBUILD completion:   8 sec

 

Writing NGDBUILD log file "test_LED.bld"...

 

NGDBUILD done.

 

Process "Translate" completed successfully

 

Started : "Map".

Running map...

Command Line: map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o test_LED_map.ncd test_LED.ngd test_LED.pcf

Using target part "6slx150tfgg676-3".

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

INFOSmiley Frustratedecurity:56 - Part 'xc6slx150t' is not a WebPack part.

INFOSmiley Frustratedecurity:60 - The XILINXD_LICENSE_FILE environment variable is set to

'C:\Xilinx'.

INFOSmiley Frustratedecurity:62 - The LM_LICENSE_FILE environment variable is set to

'C:\Xilinx'.

INFOSmiley Frustratedecurity:68 - For more information or for assistance in obtaining

a license, please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses".)

INFOSmiley Frustratedecurity:68a - user is JCR, on host QUADRIVE-A025ED.

WARNINGSmiley Frustratedecurity:9b - No 'ISE' feature version 2013.10 was available for part

'xc6slx150t'.

ERRORSmiley Frustratedecurity:12 - No 'xc6slx150t' feature version 2013.10 was available (-5),

     so 'WebPack' may not be used.

----------------------------------------------------------------------

No such feature exists.

Feature:       ISE

License path:

C:\Xilinx\Xilinx.lic;C:/.Xilinx\Xilinx.lic;C:/.Xilinx\Xilinx_14_7.lic;C:\Xilinx\

14.7\ISE_DS\ISE\/coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE\/cor

egen/core_licenses\XilinxFree.lic;C:\Xilinx\14.7\ISE_DS\EDK/data/core_licenses\X

ilinx.lic;

FLEXnet Licensing error:-5,357

For further information, refer to the FLEXnet Licensing documentation,

available at "www.flexerasoftware.com".No such feature exists.

Feature:       xc6slx150t

License path:

C:\Xilinx\Xilinx.lic;C:/.Xilinx\Xilinx.lic;C:/.Xilinx\Xilinx_14_7.lic;C:\Xilinx\

14.7\ISE_DS\ISE\/coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE\/cor

egen/core_licenses\XilinxFree.lic;C:\Xilinx\14.7\ISE_DS\EDK/data/core_licenses\X

ilinx.lic;

FLEXnet Licensing error:-5,357

For further information, refer to the FLEXnet Licensing documentation,

available at "www.flexerasoftware.com".

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

ERROR:Map:258 - A problem was encountered attempting to get the license for this

 

Design Summary

--------------

Number of errors   :   1

Number of warnings :   0

 

Process "Map" failed

Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: Mapping step does not work in my kit

Your log file shows you are using the WebPack software. The LX150T device is not supported by WebPack, you need to install the full version of the software device locked to the LX150T device.

Visitor
Posts: 7
Registered: ‎09-07-2014

Re: Mapping step does not work in my kit

Thanks for finding the problem. Now the big question. Do I need to pay more for this full version? Because in AVNET site it is stated that I would receive all necessary tools to work with the kit I bought.

Best regards

João

Avnet Employee (Star Contributor)
Posts: 511
Registered: ‎05-05-2009

Re: Mapping step does not work in my kit

You get full version of the tool device locked to lx150t. Please contact Avnet local office to obtain the software.