Posts: 1
Registered: ‎07-07-2011

MIG on PLB bus for DDR3 access

Hi All,

I'm trying to access towards the DDR3 for the LX75T Development board, but it doesn't work.

My design is based on PLB bus and I need your help in order to catch the correct parameters to configure the MIG properly.

Could someone help me?


Thanks in advanced


Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: MIG on PLB bus for DDR3 access

The issue with running your MIG-generated design may be a board-level issue.  The errata for this board (posted on the DRC) describes a known problem with the DDR3 interface and the default bitgen settings.  By default the bitgen settings for any XPS project attach pulldowns to any unused signals on the FPGA.  This breaks the FPGA designs using the MCBs.  To fix this, change the bitgen settings to allow unused pins to float.  Add this line to the bitgen settings file (bitgen.ut) of your project:


-g UnusedPin: Pullnone  (remove the space between the ':' and 'P')


This should fix the problem.



Tom Curran