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Visitor
Posts: 5
Registered: ‎07-22-2010

MIG parameters for SP6 LX75T

Hi,

Using DDR3 connected to Bank 4.

Generating DDR3 controller using MIG 13.2

 

Can I have correct MIG settings?

 

 

Manish 

Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: MIG parameters for SP6 LX75T

You can use the attached document to use MIG to configure and generate a DDR3 MCB design for MCB4 of the S6LX75T board.

--
Tom Curran
Visitor
Posts: 5
Registered: ‎07-22-2010

Re: MIG parameters for SP6 LX75T Kit

Thanks for the pointer.

But the speed grades of DDR3 memories mentioned in MIG LAB document you shared and the one in user guide from Avnet site are different:

MIG_LAB pdf says  MT41J64M16XX-187E

Userguide says:    MT41J64M16JT-15E:G

 

which one is correct? 

 

PS: Unfortunately the board is not with me, so couldn't figure-out which one is actually on board. 

Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: MIG parameters for SP6 LX75T Kit

I know the Lab1 PDF I sent will build a working MCB interface, so use those parameters.  I suspect the User Guide is incorrect.  You could also examine the Micron memory device on the board and use their device decoder (http://www.micron.com/support/fbga.html) to determine the exact device installed on the board.

 

I hope this helps.

 

--Tom

 

--
Tom Curran
Visitor
Posts: 5
Registered: ‎07-22-2010

Re: MIG parameters for SP6 LX75T Kit

Hi,

I got correct memory part number from the board.

 

However, its not working on board. . Facing a strange problem:

 

* Have brought "calibration_done" signal to LED, it glows after FPGA is configured. 

* But when "reset" is pressed calllibration_done goes oFF and doesn't come up again.

 - Push button, LED poartites are correct.

 

Hence tried simulation

 

Tool: ISE 13.2

Mode of Usage: Non-EDK.  We are generating DDR3 controller for memory connected to M4 bank using MIG tool.

Understanding:

* In MIG setting page, we request 333.33 MHz clock and select input clock as single ended.

  Hence, once MIG generates core (.xco in our case)  it assumes someone will give 333.33 MHz clock to it.

  Internal PLLs are configured with settings to generate other clocks like sys_clock_2x, sys_clock_2x_180, usr_clk, calib_clk       etc.

* On board there is 100 MHz oscillator.

  Hence we generated 333.33 MHz using DCM and then fed it to MIG generated core.  

 

* Is this scheme fine?

 

* With such scheme, behave and post-translate simulations work.

  We have basic peek-poke test bench which write some data into memory model and reads back.

  Same flow at post-map and post-par doesn’t work.  

* In this simulation,  DDR clock pins (dram_ck and dram_ck_n) are not toggling at all.—tied to logic ‘0’.

 Tapped ports of PLL in simulation, they toggle at correct frequency. 

 

 

* Can't share RTL. Will contact local Avnet FAE if other details are needed for solving the problem. 

 

Manish 

Avnet Employee (Super Contributor)
Posts: 79
Registered: ‎04-17-2009

Re: MIG parameters for SP6 LX75T Kit

The issue with running your MIG-generated design may be a board-level issue.  The errata for this board (posted on the DRC) describes a known problem with the DDR3 interface and the default bitgen settings.  By default the bitgen settings for any XPS project attach pulldowns to any unused signals on the FPGA.  This breaks the FPGA designs using the MCBs.  To fix this, change the bitgen settings to allow unused pins to float.  Add this line to the bitgen settings file (bitgen.ut) of your project:

 

-g UnusedPin: Pullnone  (remove the space between the ':' and 'P')

 

This should fix the problem.

 

--Tom

--
Tom Curran
Visitor
Posts: 5
Registered: ‎07-22-2010

Re: MIG parameters for SP6 LX75T Kit

Thanks. I will try this on board.

Btw, dou you have any clue about the simulation problem I am facing: 

Tool: ISE 13.2

Mode of Usage: Non-EDK.  We are generating DDR3 controller for memory connected to M4 bank using MIG tool.

Understanding:

* In MIG setting page, we request 333.33 MHz clock and select input clock as single ended.

  Hence, once MIG generates core (.xco in our case)  it assumes someone will give 333.33 MHz clock to it.

  Internal PLLs are configured with settings to generate other clocks like sys_clock_2x, sys_clock_2x_180, usr_clk, calib_clk       etc.

* On board there is 100 MHz oscillator.

  Hence we generated 333.33 MHz using DCM and then fed it to MIG generated core.  

 

* Is this scheme fine?

 

* With such scheme, behave and post-translate simulations work.

  We have basic peek-poke test bench which write some data into memory model and reads back.

  Same flow at post-map and post-par doesn’t work.  

* In this simulation,  DDR clock pins (dram_ck and dram_ck_n) are not toggling at all.—tied to logic ‘0’.

 Tapped ports of PLL in simulation, they toggle at correct frequency. 

 

Visitor
Posts: 5
Registered: ‎07-22-2010

Re: MIG parameters for SP6 LX75T Kit

Hi Tom,

-g UnusedPin: Pullnone    seting helped. It worked on board.