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Contributor
Posts: 10
Registered: ‎02-27-2011

"PCIe PIO Demo" using "Spartan-6 Integrated Block for PCI Express" V2.4 (AXI4-Stream)


Hello,

- Attached an archive that is a modified version of the
  "PCIe PIO Demo" project that is using the "Spartan-6
  Integrated Block for PCI Express" V2.4 (AXI4-Stream interface),
  instead of the (legacy) "Spartan-6 Integrated Block for
  PCI Express" V1.4 (TRN interface).

- Modified RTL files are in "<project>/src" directory.

- Modified batch files and "ucf" file are in
  "<project>/ise_aes-s6pcie-lx75t-g\uf" directory.

- There is also an ISE and iMPACT project files in
  "<project>/ise_aes-s6pcie-lx75t-g" directory, for those that
  want to built and program using GUI.


- Remarks:
      - Use ISE V14.1

    - Contain only Verilog-HDL solution.

    - Software is not included, since this
      demo use the same software as the original
      demo.

    - Successfully tested on the AES-S6PCIE-LX75T-G development kit.


Enjoy,

Claude Sylvain
Electro-Technica inc.


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Contributor
Posts: 10
Registered: ‎02-27-2011

Re: "PCIe PIO Demo" using "Spartan-6 Integrated Block for PCI Express" V2.4 (AXI


- Attached another file ("implement.bat.zip") that fix an error in
  "<project>\ise_aes-s6pcie-lx75t-g\uf\implement\implement.bat"
  Without that fix, generated ".bit" files are not functional,
  when using "implement.bat" to built the project.

Claude Sylvain
Electro-Technica inc.