06-29-2012 08:04 AM
- Attached an archive that is a modified version of the
"PCIe PIO Demo" project that is using the "Spartan-6
Integrated Block for PCI Express" V2.4 (AXI4-Stream interface),
instead of the (legacy) "Spartan-6 Integrated Block for
PCI Express" V1.4 (TRN interface).
- Modified RTL files are in "<project>/src" directory.
- Modified batch files and "ucf" file are in
- There is also an ISE and iMPACT project files in
"<project>/ise_aes-s6pcie-lx75t-g" directory, for those that
want to built and program using GUI.
- Use ISE V14.1
- Contain only Verilog-HDL solution.
- Software is not included, since this
demo use the same software as the original
- Successfully tested on the AES-S6PCIE-LX75T-G development kit.
06-29-2012 01:08 PM
- Attached another file ("implement.bat.zip") that fix an error in
Without that fix, generated ".bit" files are not functional,
when using "implement.bat" to built the project.