06-04-2013 09:12 AM
I'm considering using the MicroBoard to sample and process a serial bitstream at the highest possible rate. I have a theoretical understanding of the Spartan6 LX9 architecture, and would like to know what is and isn't possible with the Microboard.
I would like to sample two single-bit streams of data connected via one of the PMOD interfaces at 1GSa/s. There is no external clock (therefore no synchronisation constraints), so the clock will either be generated inside the FPGA one way or another.
The requirement to sample a bitstream at 1GSa/s can, in general, be met using the standard Xilinx SERDES "macro". Can the SERDES macro be used with signals on one of the PMOD connectors?
The requirement for a 1GHz clock used for sampling can, in general, be met in the FPGA. Can the Microboard generate a 1GHz internal clock, directly or indirectly? If not, are there sufficient spare FPGA resources for me to supply my own clock via the same PMOD connector? I appreciate that I'll have to turn off the spread spectrum clock features.
Thanks in advance for any pointers you can provide.
06-04-2013 03:12 PM
The Microboard loaded with a -2 speed grade device, thus is only capable of a 500Mbps differential reciever.
The board has TI clock generator which would like need to be configured to provide a high-frequency, clean clock to
the PLL's in the FPGA. I don't know what frequency is required but running through the clocking wizard will tell you
what the ideal frequency is to handle 500Mbps.
That said, what the FPGA can do is only half the battle. The board would need differentially routed which was not the
intent of the LX9 MicroBoard. The Pmods where placed mostly to take advantage of the vast Pmod ecosystem.
06-05-2013 04:29 AM
Thank you for the reply.
I hadn't noticed it was a -2 speed part, but I think that limits me to 950MSa/s in the 8bit mode.
I don't have access to the clocking wizard, so I'm afraid I can't check that out.
The PCB layout is potentially a significant issue, as you note. Is there anywhere I can see a schematic and preferably a pcb layout?
N.B. when logged in I cannot see any of the details of the board: you website repeatedy loops trying to load about 3 different pages. This happens in three different browsers, so I don't think it is a browser issue.
(I'm clicking the view details button in the design centre tab on this page)
06-05-2013 05:14 AM
When you write
The board would need differentially routed which was not the intent of the LX9 MicroBoard
do you mean
I might be able to work-around (1), but could not work around (2).
06-05-2013 09:41 AM
If you have previously logged into the Avnet DRC, your login will go stale and you will see the phenonmenon you mention. You need to close your browser, then re-launch, then try again. Sorry for the issue. It's frustrating to all of us that work with the Avnet Boards as well.
Once you do that, hopefully you can get on and get the schematics. You'll find that all 16 I/Os connected to the Dual 2x6 Pmods are differential capable. Jayson is stating that neither the pairs were routed differentially, nor was any length matching followed during PCB layout.
The DRC will have PDF schematics and layout. You can request the PCB database from your local Avnet/Silica FAE.
06-05-2013 02:25 PM
It seems that the core of the problem is that some of your systems have problems with the email associated with tggzzz - even though your system accepted it and has sent password resets to it! Changing to a different email address is more successful.
Thanks for a clear answer to the important technical question; I can now see the PCB layouts and will determine whether I can work with their limitations.
Thanks also for the candour about the "suboptimal" aspect of your systems; it gives extra confidence in your other statements!
09-05-2013 11:26 AM
I am currrently solving the same problem, I have found that I can output a clock at ~950 MHz using BLVDS_25 and ODDR2 on PMOD 1 pins 9-10, and receive on PMOD 2 pins 9-10 using LVDS_33. 9 and 10 appear the best routes, but are still quit noisy... have not completely resolved the issues, and is complicated by not using bank 0 or 2, not using clock inputs, and not using differential routing...