12-03-2012 02:09 PM
We're using a number of LX9 micro boards in a control application at the Advanced Light Source here at Lawrence Berkeley National Laboratory. I'd like to add a watchdog reset function, but I don't see anything on the schematic that would let the FPGA (U4) simulate the effect of a reset button push (SW4).
Where can I direct the 'reset' line of an AXI Watchdog Timer IP block to most closely simulate a power-on reset?
12-04-2012 04:48 PM
SW4 will initiate a PROG toggle, which will clear the LX9 and reconfigure.
SW5 is a user-accessible push-button tied to LX9 I/O V4. If you're just trying to simulate a Power Good signal, then you could use this button.
Neither of these are tied to the board's Power Good. There is a net coming off U7 (TPS65708) which is the Power Good signal (POWER_GOOD_LED). You could wire from this signal over to SW5.
05-22-2015 10:18 AM
The schematic shows a capacitor to ground at V4, but with the value "DNP", which I guess is "do not populate". The UCF file Avt_S6LX9_MicroBoard_UCF_110804 suggests that the Reset_N logic has been changed to Reset on high at some point. However, that would require a capacitor to VDD to make sure that we get a good POR. So how does that work?
05-22-2015 01:10 PM
The USER_RESET signal is tied to general purpose I/O V4. It is not a power-on reset for the device. It's intended for use as a reset for your logic. We recommend you use de-bouncing inside your FPGA for it. If you would like to populate capacitor C89, you are welcome to do that as the pads are available.
The note in the UCF is simply a clerical thing. At one time, the net was called USER_RESET_N, even though it is high enabled. We did not change the circuit. We merely changed the net name to remove the "_N" since pushing the button delivers a logic high to IO V4.
05-26-2015 10:59 AM
I wonder why this was ever changed. It makes perfect sense to have a capacitor to GND (and resistor to VDD), which ensures POR (assuming RESET at low), and then a pushbutton that shorts it (i.e. to GND) would deliver a RESET_N. Such capacitor would even solve the debounce problem.
Anwyay, thanks for explaining what the board has. I guess we'll just have to work with that and not rely on any external POR.
05-26-2015 02:12 PM
To reiterate, the circuit was never changed. It was a naming convention change only.
If you would like to have the capacitor, simply solder one on. The pads are there.
Regarding POR, read Chapter 4 of UG394.
Spartan-6 FPGAs have a built-in power-on reset (POR) circuit that monitors the three
power rails required to successfully configure the FPGA (see Figure 4-1). At power-up, the
POR circuit holds the FPGA in a reset state until the VCCINT, VCCAUX, and VCCO_2 supplies
reach their respective input threshold levels. A time tPOR after all three supplies reach their
respective thresholds, the POR reset is released and the FPGA begins its configuration