11-19-2015 11:49 AM
I wanted to post some additional related material I was pointed to by a few other FPGA Engineers which may be useful to others who stumble across this thread in the future.
Here is a white paper from the folks at Fujitsu entitled "How Spread Spectrum Clock Generators Accelerate FCC Certification of System Designs" which gives some background on why a system designer would want to use a spread spectrum clock in their electronic design:
Another reason to use a clock manganagment element (such as DCM or MMCM or PLL) in FPGA design is to protect against spurious transients on the external clock resulting in metastable conditions within fabic. Here is an excellent article on metastability from the folks at ADIUVO Engineering:
Hopefully someone finds this information useful for accelerating their own FPGA designs.