Regular Visitor
Posts: 3
Registered: ‎08-20-2009

REG schematic verification wrt K7 and OMAP L138 .

Hi ,

We are supporting  a  customer Board with K7  Xc7k160T-1FBG676I and TI OMAP-L138 processor.

We are in the process of schematic review and comparing customer schematic wrt ADS- S6-OMAP schematic .

As we understand fom the TI ref manual  page 1518  mentions uPP can be  the connectivity b/n TI and Xilinx FPGA via EMIF.


We need help in understanding  the basic checksum to verify  Customer schematic specific to EMIF and related signals wrt FPGA.

Any pointers higly appreciated.





Avnet Employee (Star Contributor)
Posts: 471
Registered: ‎04-16-2009

Re: REG schematic verification wrt K7 and OMAP L138 .



The uPP and EMIF interfaces are two distinct interfaces.

Here is an excerpt from the “S6-OMAP – Inter-Communication Reference Design Tutorial”, that gives an overview of when each interface could be used, as well as a working ref design example, including VHDL source code.



The S6-OMAP Co-Processing Kit implements four interfaces between the OMAP-L138 processor and the Spartan-6 FPGA, as shown in the following figure.


{see attached image} 


Figure 1 – Inter-Communication Interfaces – Block Diagram


In order to determine how to use these interfaces, it is important to understand each of their strengths and weaknesses.






SOM can be master

FPGA can be master




Implements addressing


Peak Bandwidth





Table 1 – Inter-Communication Interfaces – Strengths and Weaknesses


From the table above, it should become obvious that each interface is ideal for different tasks:

  • I2C & SPI => Control
    • Configuration of FPGA design
  • UPP => High-Bandwidth data streaming to/from FPGA
    • Real-time I/O to the FPGA’s expansion ports (ALI, FMC, …)
  • EMIFA => medium-bandwidth data transfers to FPGA
    • Managing large parameter sets in FPGA (ie. Look up tables)



[1] UPP Peak Bandwidth calculated as follows : 75 MHz * 16 bits = 1.2 Gbps

[2] EMIFA Peak Bandwidth calculated as follows : 25 MHz * 16 bits / (4 cycles/transfer) = 100 Mbps