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Visitor
Posts: 2
Registered: ‎02-16-2013

Re: Change of the CDCE72010 register settings in the reference design

Hi

Thank you for the code with the auto-calibration blocks. When I am using this code with 245.76 MSPS as the sampling rate , it works fine. But when I am using the same old cdce72010_init_int_491_52MHz.coe'  to have a 61.44MSPS for the SPI registers, (CLk = 61.44 MHz and CLKDIV is 30.72MHz in the ISERDESE1 ) the output signals from ADCs are not ok.  I am using this modified reference design to use the calibration blocks for ADC's.I also enabled the low speed mode for the ADC62P49.Any idea?

Contributor
Posts: 12
Registered: ‎02-05-2012

Re: Change of the CDCE72010 register settings in the reference design

Hello, 

 

I tried to modify the IF frequency from 12 MHz to a higher one, say at about 30 MHz at the dds_ddc_v6 IP core using the Core generator GUI but I got the following error 

 

ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - "Unknown" Line 0: Save failed due to mkdir failure
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'dds_ddc_v6'. Failed executing Tcl generator.

 

Do I need to do this on a linux OS? 

 

regards,

Regular Visitor
Posts: 2
Registered: ‎09-24-2012

Re: Change of the CDCE72010 register settings in the reference design

hello,

i would like to change DUC frequency as 70 Mhz and when it is sampled i want to output  400 mhz.

how can i do it in the sample design?

could you help me, please?

thnx