07-25-2012 09:24 AM
I encountered a very strange configuration error of the DAC for several times with the demo file.
The problem is that after loading the bit-file to the FPGA the DAC sometimes interprets the incoming data as offset-binary and not as two's complement (DAC's CONFIG1 register). I checked the data in the DAC ICON core where they are fine. However in a scope and in the ADC ICON core you get the same strange results. I attached a screenshot of the data taken with a scope.
What is also strange is that after a new configuration of the FPGA the data are interpreted in the two's complement format. I am not able to explain why this can happen after a new configuration but not after a new compilation of the design.
Did anyone experience the same problem? Thank you very much in advance.