Regular Visitor
Posts: 3
Registered: ‎03-19-2012

LVDS buffer in system generator for FMC150 ADC

Hi , 

I'm trying to make JTAG cosimulation in system generator for my virtex-6 DSP kit. My problem is the LVDS outputs of the ADC which should be input to the FPGA, I made the LVDS buffer in vhdl , and imported it to system generator into a blackbox. I set the constraints for the inputs from ADC and set them as non-memory mapped ports. but now I get an error when I implement for JTAG cosim. the error is mainly 


ERROR:NgdBuild:770 - IBUF 'ibuf_CHA_N/ibuf_array[6].u1' and IBUFDS 
'adc_try_x0/adc_lvdsddr_to_sdr/adc_data_a[6].ibufds_inst' on net 
'ibuf_CHA_N_o(6)' are lined up in series. Buffers of the same direction 
cannot be placed in series.



I believe its due to the JTAG cosim puts IOBs automatically for the inputs from the ADC during synthesis, and my blackbox already contains LVDS buffers. Can I stop the synthesizer from doing this ? or is there any way to work around this ? 


Thanks in advance,