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Posts: 2
Registered: ‎02-01-2012

Platform Flash Pins Access




Im currently trying to use the XCF128X platform flash on board the ML605 for fpga configuration and user data storage. Nevertheless I have found myself limited in the use of this memory cause of the lack of access to signals that drive it. The clock signal that drives the XCF128X is supposed to be connected to a K8 pin of the FPGA but I get a message when running the MAP saying:


LOC constraint K8 on <name> is invalid: No such site on the
   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.


Lack of acces to the clock that drives the memory makes syncing my code with the data being read from the memory quite hard.


I also have the same problem with the signal READY_WAIT, vital signal to control memory access, which is on P8 o fthe FPGA and displays the same message when running MAP.


Am I doing something wrong or is there no acces to these signals? In the schematic of the ML605 it is not that obvious if there is a conection to the FPGA of these signals and that is why I dont know if I should I bypass this error.


Anyone with a posible solution or recomendation?