02-24-2012 02:13 PM
When I copy the entire FMC150-ML605 demo to a fresh workspace (renaming the .bit file to save it from being overwritten) and run duc_ddc_umts_virtex6.xise through logic synthesis and implementation, the new resulting .bit file does not work. The MMCM lock lights do not even light up. I have not changed the .ucf or any of the .vhd source files. Am I perchance bumping into a tool version issue or something? I am running the 64-bit version of ISE 13.2.
If I load the target device w/ the original .bit file, the lights come on, and chipscope works fine.
What else should I be checking?
02-27-2012 08:46 AM
Latest V6 DSP Kit reference design is here:
File name: virtex6dsp_rtl_reference_design_tutorial_13_1_Dec31_2011.zip
Website link: https://avnet.egnyte.com/h-s/20120214/745d5eb81ccf4
I suspect the non-functional 13.2 bitfile is due to a known issue beyond ISE 13.1, which may be resolved with the bitgen option -g next_config_addr set to "None" instead of "0x00000". For more details: http://www.xilinx.com/support/answers/41821.htm
Furthermore, as noted on page 12, step 12) of the 'Getting Started Guide', the ZIP archive should be extracted to the root C:\ drive. This is due to a limitiation of Xilinx Core Generator FIR Compiler which requires absolute paths to .COE files. The FIR Compiler IP cannot be properly re-generated if the .COE file isn't found in it's expected location.
Technical Marketing Director, DSP
02-28-2012 11:43 AM
Thanks -- I think the file directory thing is the "root" of the problem. Is there a reasonable way to relax the Core Gen FIR requirement that everything be up at root? I like to organize my work much more hierarchically than that.
02-28-2012 02:11 PM
I tried again -- still no luck.
I unzipped a fresh copy of the project to root. I renamed the .bit file, made a minor edit in the comment lines of the top level .vhd file, and resynthesized. Chipscope claims units 0, 1, 2, and 3 no longer exist. I do see a couple of ominous synthesis warning messages, including: ila_adc_cali remains a black box since it has no binding entity, and I suspect this is at the root of my problem. What am I doing wrong, and how do I fix this?
02-28-2012 03:12 PM
In synthesis I am getting warnings that various cores are being black boxed because of lack of binding. This is presumably the problem, but I do not know how to fix it.