Posts: 1
Registered: ‎10-17-2011


I have a Virtex-6 development kit with FMC150 daughter board, and I am running ISE 13.1 .

I have instaled and ran "virtex6dsp_getting_started_reference_design" with success, however I have not been able to see any signal on J56 output after a successfull routing of mmcm or mmcm_adac output clocks.

Are these outputs alive  or there is a trick to bring the clocks out to the IO?

Regular Contributor
Posts: 46
Registered: ‎07-09-2009

Re: Clocks_OutPut_Buffers

You say you are looking for a "trick to bring the clocks out to the IO"? There should be no need to do this; proper functionality of the design can be verified with data capture through ChipScope as explained in the Getting Started Guide. If ChipScope is capturing data, then the MMCM is working. Furthermore, status of the PLLs are reflected at the LEDs for both FMC150 (CDCE72010) and FPGA MMCMs.


In Tutorial Lab 2 – Verifying the RTL DUC / DDC in Hardware with the Data Converters Using ChipScope, Step 7 figure shows LED 5,6,7 on will indicate lock on the PLL for the FMC150 and two MMCMs in the FGPA, respectively.  This excerpt is from RTL-AES-V6DSP2-LX240T-G-13_1-v3.pdf. If these LEDs don't show PLL 'Lock' from the reference design bitstream out of the box, then there is a defect with the kit.


It is beyond the scope of the DSP Reference Design Kit to pull these clocks out to GPIO on the ML605.  This may be addressed better by discussion with your local FAE or opening a case with Avnet Centralized Technical Support.