04-30-2013 02:09 PM
I have a Kintex-7 FPGA DSP Development kit and have been trying to run the QPSK Symbol Timing Recovery demonstration from the "Using Xilinx System Generator for DSP with Simulink and HDL Coder" webinar from The Mathworks website. I was successful in getting the Algorithm Validation in Simulation (Simulink only) and the Hardware Co-Simulation to work as described in the webinar. Also, I was able to get the Rx section converted to VHDL and encapsulated in a System Generator Black Box. This is where the webinar discussion skips ahead. I have been unable to get the demonstration to run on the FPGA using the Kintex-7 "Deployment" mode - where all of the models are implemeted in the actual FPGA hardware. Specifically, there is no mention in the webinar video as to where to connect the Clock, Clock Enable, and Reset lines on the Black Box. If anyone knows where the infomation to complete the design and run it using the "Deployment" mode may be found, I would greatly appreciate the answer.
Solved! Go to Solution.
05-06-2013 06:06 AM
A 2nd MathWorks webinar focusing on 'Deployment mode' for the QPSK Symbol Timing Recovery with the Kintex-7 DSP Kit is planned for late May. It will address the practical implementation issues that you mentionned. E-mail notification will be sent to all K7 DSP Kit users prior to the webinar.
05-23-2013 01:04 PM
I have watched the two webinars several times while working with the FPGA kit. To me, there still seems to be some important steps in the process that are missing. Can you make the final design files to get the QPSK example to run on the FPGA with the DACs & ADCs available?
02-01-2014 07:25 PM
Have you solved this problem? I am seeing another problem in that the Zynq SDR demo implements the Symbol Timing Generator in HDL Coder which I do not have a license for. I'm looking for QPSK Symbol Timing Recovery in System Generator for Simulink, that I can compile into the Zynq FPGA.